Lines Matching +full:clock +full:- +full:indices
1 // SPDX-License-Identifier: GPL-2.0+
8 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 compatible = "fsl,imx8q-pcie";
19 reg-names = "dbi", "config";
22 #interrupt-cells = <1>;
24 interrupt-names = "msi";
25 #address-cells = <3>;
26 #size-cells = <2>;
30 clock-names = "dbi", "mstr", "slv";
31 bus-range = <0x00 0xff>;
33 interrupt-map = <0 0 0 1 &gic 0 73 4>,
37 interrupt-map-mask = <0 0 0 0x7>;
38 num-lanes = <1>;
39 num-viewport = <4>;
40 power-domains = <&pd IMX_SC_R_PCIE_A>;
41 fsl,max-link-speed = <3>;
46 compatible = "fsl,imx8q-pcie";
49 reg-names = "dbi", "config";
52 #interrupt-cells = <1>;
54 interrupt-names = "msi";
55 #address-cells = <3>;
56 #size-cells = <2>;
60 clock-names = "dbi", "mstr", "slv";
61 bus-range = <0x00 0xff>;
63 interrupt-map = <0 0 0 1 &gic 0 105 4>,
67 interrupt-map-mask = <0 0 0 0x7>;
68 num-lanes = <1>;
69 num-viewport = <4>;
70 power-domains = <&pd IMX_SC_R_PCIE_B>;
71 fsl,max-link-speed = <3>;
76 compatible = "fsl,imx8qm-ahci";
81 clock-names = "sata", "sata_ref";
82 phy-names = "sata-phy", "cali-phy0", "cali-phy1";
83 power-domains = <&pd IMX_SC_R_SATA_0>;
98 pciea_lpcg: clock-controller@5f050000 {
99 compatible = "fsl,imx8qxp-lpcg";
102 #clock-cells = <1>;
103 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>;
104 clock-output-names = "hsio_pciea_mstr_axi_clk",
107 power-domains = <&pd IMX_SC_R_PCIE_A>;
110 sata_lpcg: clock-controller@5f070000 {
111 compatible = "fsl,imx8qxp-lpcg";
114 #clock-cells = <1>;
115 clock-indices = <IMX_LPCG_CLK_4>;
116 clock-output-names = "hsio_sata_clk";
117 power-domains = <&pd IMX_SC_R_SATA_0>;
120 phyx2_lpcg: clock-controller@5f080000 {
121 compatible = "fsl,imx8qxp-lpcg";
125 #clock-cells = <1>;
126 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
128 clock-output-names = "hsio_phyx2_pclk_0",
132 power-domains = <&pd IMX_SC_R_SERDES_0>;
135 phyx1_lpcg: clock-controller@5f090000 {
136 compatible = "fsl,imx8qxp-lpcg";
140 #clock-cells = <1>;
141 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
143 clock-output-names = "hsio_phyx1_pclk",
147 power-domains = <&pd IMX_SC_R_SERDES_1>;
150 phyx2_crr0_lpcg: clock-controller@5f0a0000 {
151 compatible = "fsl,imx8qxp-lpcg";
154 #clock-cells = <1>;
155 clock-indices = <IMX_LPCG_CLK_4>;
156 clock-output-names = "hsio_phyx2_per_clk";
157 power-domains = <&pd IMX_SC_R_SERDES_0>;
160 pciea_crr2_lpcg: clock-controller@5f0c0000 {
161 compatible = "fsl,imx8qxp-lpcg";
164 #clock-cells = <1>;
165 clock-indices = <IMX_LPCG_CLK_4>;
166 clock-output-names = "hsio_pciea_per_clk";
167 power-domains = <&pd IMX_SC_R_PCIE_A>;
170 sata_crr4_lpcg: clock-controller@5f0e0000 {
171 compatible = "fsl,imx8qxp-lpcg";
174 #clock-cells = <1>;
175 clock-indices = <IMX_LPCG_CLK_4>;
176 clock-output-names = "hsio_sata_per_clk";
177 power-domains = <&pd IMX_SC_R_SATA_0>;
181 compatible = "fsl,imx8qm-hsio";
186 reg-names = "reg", "phy", "ctrl", "misc";
201 clock-names = "pclk0", "pclk1", "apb_pclk0", "apb_pclk1",
205 #phy-cells = <3>;
206 power-domains = <&pd IMX_SC_R_SERDES_0>, <&pd IMX_SC_R_SERDES_1>;