Lines Matching +full:imx7ulp +full:- +full:lpi2c

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2018-2019 NXP
7 /delete-node/ &adma_pwm;
8 /delete-node/ &adma_pwm_lpcg;
11 	uart4_lpcg: clock-controller@5a4a0000 {
12 		compatible = "fsl,imx8qxp-lpcg";
14 		#clock-cells = <1>;
17 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
18 		clock-output-names = "uart4_lpcg_baud_clk",
20 		power-domains = <&pd IMX_SC_R_UART_4>;
24 		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
27 		interrupt-parent = <&gic>;
30 		clock-names = "per", "ipg";
31 		assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>;
32 		assigned-clock-rates = <24000000>;
33 		power-domains = <&pd IMX_SC_R_I2C_4>;
37 	i2c4_lpcg: clock-controller@5ac40000 {
38 		compatible = "fsl,imx8qxp-lpcg";
40 		#clock-cells = <1>;
43 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
44 		clock-output-names = "i2c4_lpcg_clk",
46 		power-domains = <&pd IMX_SC_R_I2C_4>;
49 	can1_lpcg: clock-controller@5ace0000 {
50 		compatible = "fsl,imx8qxp-lpcg";
52 		#clock-cells = <1>;
55 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
56 		clock-output-names = "can1_lpcg_pe_clk",
59 		power-domains = <&pd IMX_SC_R_CAN_1>;
62 	can2_lpcg: clock-controller@5acf0000 {
63 		compatible = "fsl,imx8qxp-lpcg";
65 		#clock-cells = <1>;
68 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
69 		clock-output-names = "can2_lpcg_pe_clk",
72 		power-domains = <&pd IMX_SC_R_CAN_2>;
78 	#dma-cells = <3>;
79 	dma-channels = <22>;
80 	dma-channel-mask = <0xf00>;
103 	power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
131 	dma-channels = <10>;
142 	power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
155 	fsl,clk-source = /bits/ 8 <1>;
161 	assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>;
162 	fsl,clk-source = /bits/ 8 <1>;
168 	assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>;
169 	fsl,clk-source = /bits/ 8 <1>;
173 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
175 	dma-names = "rx","tx";
179 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
181 	dma-names = "rx","tx";
185 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
187 	dma-names = "rx","tx";
191 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
193 	dma-names = "rx","tx";
197 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
201 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
205 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
209 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";