Lines Matching +full:1 +full:e40000

47 		#address-cells = <1>;
85 		A53_1: cpu@1 {
231 			#address-cells = <1>;
242 			port@1 {
243 				reg = <1>;
334 			thermal-sensors = <&tmu 1>;
374 		#address-cells = <1>;
375 		#size-cells = <1>;
451 				#address-cells = <1>;
462 				port@1 {
463 					reg = <1>;
530 			#address-cells = <1>;
531 			#size-cells = <1>;
605 				#thermal-sensor-cells = <1>;
671 				#address-cells = <1>;
672 				#size-cells = <1>;
711 				#clock-cells = <1>;
750 				#clock-cells = <1>;
775 				#reset-cells = <1>;
787 					#address-cells = <1>;
795 					pgc_pcie_phy: power-domain@1 {
946 			#address-cells = <1>;
947 			#size-cells = <1>;
1030 			#address-cells = <1>;
1031 			#size-cells = <1>;
1037 				#address-cells = <1>;
1038 				#size-cells = <1>;
1042 					#address-cells = <1>;
1053 					dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1059 					#address-cells = <1>;
1070 					dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
1076 					#address-cells = <1>;
1087 					dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
1161 				#address-cells = <1>;
1162 				#size-cells = <1>;
1192 				#address-cells = <1>;
1202 				#address-cells = <1>;
1212 				#address-cells = <1>;
1222 				#address-cells = <1>;
1260 				#address-cells = <1>;
1270 				#address-cells = <1>;
1330 				#address-cells = <1>;
1405 			#address-cells = <1>;
1406 			#size-cells = <1>;
1412 				#address-cells = <1>;
1413 				#size-cells = <1>;
1426 					dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
1573 						     /* XCVR IRQ 1 */
1614 				#clock-cells = <1>;
1615 				#reset-cells = <1>;
1638 			#interconnect-cells = <1>;
1657 			#address-cells = <1>;
1658 			#size-cells = <1>;
1674 					#address-cells = <1>;
1685 					port@1 {
1686 						reg = <1>;
1708 					#address-cells = <1>;
1711 					port@1 {
1712 						reg = <1>;
1726 				fsl,blk-ctrl = <&media_blk_ctrl 1>;
1730 					#address-cells = <1>;
1733 					port@1 {
1734 						reg = <1>;
1749 			mipi_csi_0: csi@32e40000 {
1767 					#address-cells = <1>;
1774 					port@1 {
1775 						reg = <1>;
1802 					#address-cells = <1>;
1809 					port@1 {
1810 						reg = <1>;
1836 					#address-cells = <1>;
1847 					port@1 {
1848 						reg = <1>;
1896 				#address-cells = <1>;
1897 				#size-cells = <1>;
1955 				#power-domain-cells = <1>;
1968 						#address-cells = <1>;
1979 						port@1 {
1980 							reg = <1>;
2023 				#power-domain-cells = <1>;
2045 				#power-domain-cells = <1>;
2053 				#interrupt-cells = <1>;
2054 				fsl,channel = <1>;
2070 					#address-cells = <1>;
2080 					port@1 {
2081 						reg = <1>;
2121 				reg-io-width = <1>;
2125 					#address-cells = <1>;
2136 					port@1 {
2137 						reg = <1>;
2175 			num-lanes = <1>;
2179 			#interrupt-cells = <1>;
2181 			interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2210 			num-lanes = <1>;
2281 			#power-domain-cells = <1>;
2353 			#address-cells = <1>;
2354 			#size-cells = <1>;
2396 			#address-cells = <1>;
2397 			#size-cells = <1>;
2422 			mboxes = <&mu2 2 0>, <&mu2 2 1>,
2423 				<&mu2 3 0>, <&mu2 3 1>;