Lines Matching +full:clk +full:- +full:pins
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2020-2021 TQ-Systems GmbH
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include "imx8mm-tqma8mqml.dtsi"
14 model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
15 compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
16 chassis-type = "embedded";
27 reg_usdhc2_vmmc: regulator-vmmc {
28 compatible = "regulator-fixed";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
31 regulator-name = "VSD_3V3";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
35 enable-active-high;
36 startup-delay-us = <100>;
37 off-on-delay-us = <12000>;
41 compatible = "gpio-usb-b-connector", "usb-b-connector";
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_usb1_connector>;
46 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
49 #address-cells = <1>;
50 #size-cells = <0>;
55 remote-endpoint = <&usb1_drd_sw>;
66 gpio-controller;
67 #gpio-cells = <2>;
68 vcc-supply = <®_vcc_3v3>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_expander>;
71 interrupt-parent = <&gpio1>;
73 interrupt-controller;
74 #interrupt-cells = <2>;
79 samsung,burst-clock-frequency = <891000000>;
80 samsung,esc-clock-frequency = <20000000>;
84 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
85 fsl,clkreq-unsupported;
87 clock-names = "ref";
93 reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
94 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 3>,
95 <&clk IMX8MM_CLK_PCIE1_AUX>;
96 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
97 <&clk IMX8MM_CLK_PCIE1_CTRL>;
98 assigned-clock-rates = <10000000>, <250000000>;
99 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
100 <&clk IMX8MM_SYS_PLL2_250M>;
105 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
106 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
107 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
108 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
109 <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
110 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
111 <&clk IMX8MM_AUDIO_PLL2_OUT>;
115 clock-names = "mclk";
116 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
120 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
121 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
125 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
126 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_usbotg1>;
133 srp-disable;
134 hnp-disable;
135 adp-disable;
136 power-active-high;
137 over-current-active-low;
138 usb-role-switch;
143 remote-endpoint = <&usb_dr_connector>;
150 disable-over-current;
151 vbus-supply = <®_hub_vbus>;
157 fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x00000006>,
164 fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x00000006>,
171 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x94>;
175 fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002>,
192 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x84>,
198 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x84>,
203 fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000004>,
208 fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x40000004>,
213 fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000004>,
218 fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x40000004>,
223 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x14>;
227 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x14>;
231 fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x94>,
241 fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x16>,
246 fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x16>,
251 fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x16>,
256 fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x16>,
261 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x84>,
265 pinctrl_usb1_connector: usb1-connectorgrp {
266 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c0>;
270 fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x84>;
274 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
283 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
284 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,
293 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
294 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>,