Lines Matching +full:imx8qxp +full:- +full:dsp
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
40 #address-cells = <2>;
41 #size-cells = <0>;
43 /* We have 1 clusters with 2 Cortex-A35 cores */
46 compatible = "arm,cortex-a35";
48 enable-method = "psci";
49 next-level-cache = <&A35_L2>;
51 #cooling-cells = <2>;
52 operating-points-v2 = <&a35_opp_table>;
57 compatible = "arm,cortex-a35";
59 enable-method = "psci";
60 next-level-cache = <&A35_L2>;
62 #cooling-cells = <2>;
63 operating-points-v2 = <&a35_opp_table>;
66 A35_L2: l2-cache0 {
68 cache-level = <2>;
69 cache-unified;
73 a35_opp_table: opp-table {
74 compatible = "operating-points-v2";
75 opp-shared;
77 opp-900000000 {
78 opp-hz = /bits/ 64 <900000000>;
79 opp-microvolt = <1000000>;
80 clock-latency-ns = <150000>;
83 opp-1200000000 {
84 opp-hz = /bits/ 64 <1200000000>;
85 opp-microvolt = <1100000>;
86 clock-latency-ns = <150000>;
87 opp-suspend;
91 gic: interrupt-controller@51a00000 {
92 compatible = "arm,gic-v3";
95 #interrupt-cells = <3>;
96 interrupt-controller;
100 reserved-memory {
101 #address-cells = <2>;
102 #size-cells = <2>;
105 dsp_reserved: dsp@92400000 {
107 no-map;
112 compatible = "arm,cortex-a35-pmu";
117 compatible = "arm,psci-1.0";
121 system-controller {
122 compatible = "fsl,imx-scu";
123 mbox-names = "tx0",
130 pd: power-controller {
131 compatible = "fsl,imx8dl-scu-pd", "fsl,scu-pd";
132 #power-domain-cells = <1>;
135 clk: clock-controller {
136 compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
137 #clock-cells = <2>;
141 compatible = "fsl,imx8qxp-sc-gpio";
142 gpio-controller;
143 #gpio-cells = <2>;
147 compatible = "fsl,imx8dxl-iomuxc";
151 compatible = "fsl,imx8qxp-scu-ocotp";
152 #address-cells = <1>;
153 #size-cells = <1>;
165 compatible = "fsl,imx8qxp-sc-rtc";
169 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
171 wakeup-source;
175 compatible = "fsl,imx8dxl-sc-wdt", "fsl,imx-sc-wdt";
176 timeout-sec = <60>;
179 tsens: thermal-sensor {
180 compatible = "fsl,imx8dxl-sc-thermal", "fsl,imx-sc-thermal";
181 #thermal-sensor-cells = <1>;
186 compatible = "arm,armv8-timer";
188 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
193 thermal_zones: thermal-zones {
194 cpu-thermal {
195 polling-delay-passive = <250>;
196 polling-delay = <2000>;
197 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
212 cooling-maps {
215 cooling-device =
224 xtal32k: clock-xtal32k {
225 compatible = "fixed-clock";
226 #clock-cells = <0>;
227 clock-frequency = <32768>;
228 clock-output-names = "xtal_32KHz";
231 xtal24m: clock-xtal24m {
232 compatible = "fixed-clock";
233 #clock-cells = <0>;
234 clock-frequency = <24000000>;
235 clock-output-names = "xtal_24MHz";
239 #include "imx8-ss-cm40.dtsi"
240 #include "imx8-ss-adma.dtsi"
241 #include "imx8-ss-conn.dtsi"
242 #include "imx8-ss-ddr.dtsi"
243 #include "imx8-ss-lsio.dtsi"
244 #include "imx8-ss-hsio.dtsi"
247 #include "imx8dxl-ss-adma.dtsi"
248 #include "imx8dxl-ss-conn.dtsi"
249 #include "imx8dxl-ss-lsio.dtsi"
250 #include "imx8dxl-ss-ddr.dtsi"
251 #include "imx8dxl-ss-hsio.dtsi"