Lines Matching +full:clock +full:- +full:indices
1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
9 hsio_axi_clk: clock-hsio-axi {
10 compatible = "fixed-clock";
11 #clock-cells = <0>;
12 clock-frequency = <400000000>;
13 clock-output-names = "hsio_axi_clk";
16 hsio_per_clk: clock-hsio-per {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <133333333>;
20 clock-output-names = "hsio_per_clk";
23 hsio_refa_clk: clock-hsio-refa {
24 compatible = "gpio-gate-clock";
26 #clock-cells = <0>;
27 enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>;
30 hsio_refb_clk: clock-hsio-refb {
31 compatible = "gpio-gate-clock";
33 #clock-cells = <0>;
34 enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>;
37 xtal100m: clock-xtal100m {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <100000000>;
41 clock-output-names = "xtal_100MHz";
45 compatible = "simple-bus";
48 #address-cells = <1>;
49 #size-cells = <1>;
50 dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
53 compatible = "fsl,imx8q-pcie";
56 reg-names = "dbi", "config";
59 #interrupt-cells = <1>;
61 interrupt-names = "msi";
62 #address-cells = <3>;
63 #size-cells = <2>;
67 clock-names = "dbi", "mstr", "slv";
68 bus-range = <0x00 0xff>;
70 interrupt-map = <0 0 0 1 &gic 0 105 4>,
74 interrupt-map-mask = <0 0 0 0x7>;
75 num-lanes = <1>;
76 num-viewport = <4>;
77 power-domains = <&pd IMX_SC_R_PCIE_B>;
78 fsl,max-link-speed = <3>;
82 pcieb_lpcg: clock-controller@5f060000 {
83 compatible = "fsl,imx8qxp-lpcg";
86 #clock-cells = <1>;
87 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>;
88 clock-output-names = "hsio_pcieb_mstr_axi_clk",
91 power-domains = <&pd IMX_SC_R_PCIE_B>;
94 phyx1_crr1_lpcg: clock-controller@5f0b0000 {
95 compatible = "fsl,imx8qxp-lpcg";
98 #clock-cells = <1>;
99 clock-indices = <IMX_LPCG_CLK_4>;
100 clock-output-names = "hsio_phyx1_per_clk";
101 power-domains = <&pd IMX_SC_R_SERDES_1>;
104 pcieb_crr3_lpcg: clock-controller@5f0d0000 {
105 compatible = "fsl,imx8qxp-lpcg";
108 #clock-cells = <1>;
109 clock-indices = <IMX_LPCG_CLK_4>;
110 clock-output-names = "hsio_pcieb_per_clk";
111 power-domains = <&pd IMX_SC_R_PCIE_B>;
114 misc_crr5_lpcg: clock-controller@5f0f0000 {
115 compatible = "fsl,imx8qxp-lpcg";
118 #clock-cells = <1>;
119 clock-indices = <IMX_LPCG_CLK_4>;
120 clock-output-names = "hsio_misc_per_clk";
121 power-domains = <&pd IMX_SC_R_HSIO_GPIO>;