Lines Matching full:cmu_mif
380 <&cmu_mif CLK_SCLK_MFC_PLL>,
381 <&cmu_mif CLK_SCLK_BUS_PLL>;
393 cmu_mif: clock-controller@105b0000 { label
472 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
473 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
474 <&cmu_mif CLK_SCLK_DSD_DISP>,
475 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
476 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
477 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
478 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
479 <&cmu_mif CLK_ACLK_DISP_333>;
516 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
549 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
558 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;