Lines Matching +full:1 +full:kib
44 #address-cells = <1>;
61 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
64 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
71 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
78 cpu1: cpu@1 {
85 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
88 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
95 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
109 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
112 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
119 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
133 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
136 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
143 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
192 #address-cells = <1>;
193 #size-cells = <1>;
239 #interrupt-cells = <1>;
269 #interrupt-cells = <1>;
288 interrupts = <1>;
303 #interrupt-cells = <1>;
310 #clock-cells = <1>;
311 #reset-cells = <1>;
318 interrupts = <1>;
320 #address-cells = <1>;
330 #address-cells = <1>;
339 #interrupt-cells = <1>;
347 #interrupt-cells = <1>;
370 resets = <&dvp 1>;
372 interrupts = <1>, <2>, <3>,