Lines Matching +full:timer +full:- +full:secure

1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 	interrupt-parent = <&gic>;
13 	#address-cells = <2>;
14 	#size-cells = <2>;
17 		#address-cells = <2>;
18 		#size-cells = <0>;
21 			compatible = "arm,cortex-a53";
24 			enable-method = "psci";
25 			next-level-cache = <&l2>;
29 			compatible = "arm,cortex-a53";
32 			enable-method = "psci";
33 			next-level-cache = <&l2>;
36 		l2: l2-cache0 {
38 			cache-level = <2>;
39 			cache-unified;
45 			compatible = "arm,scmi-smc";
46 			arm,smc-id = <0x82002000>;
47 			#address-cells = <1>;
48 			#size-cells = <0>;
54 				#clock-cells = <1>;
59 				#reset-cells = <1>;
65 		compatible = "arm,cortex-a53-pmu";
68 		interrupt-affinity = <&cpu0>, <&cpu1>;
72 		compatible = "arm,psci-1.0", "arm,psci-0.2";
76 	reserved-memory {
77 		#address-cells = <2>;
78 		#size-cells = <2>;
82 		scmi0_shm: scmi-shmem@800 {
83 			compatible = "arm,scmi-shmem";
88 	timer {
89 		compatible = "arm,armv8-timer";
90 		interrupts = /* Physical Secure PPI */
93 			     /* Physical Non-Secure PPI */
105 		compatible = "simple-bus";
106 		#address-cells = <1>;
107 		#size-cells = <1>;
110 		gic: interrupt-controller@410000 {
111 			compatible = "arm,gic-400";
116 			#interrupt-cells = <3>;
117 			#address-cells = <0>;
118 			interrupt-controller;
128 			reg-shift = <2>;
138 			reg-shift = <2>;
144 			compatible = "snps,designware-i2c";
149 			#address-cells = <1>;
150 			#size-cells = <0>;
155 			compatible = "snps,designware-i2c";
160 			#address-cells = <1>;
161 			#size-cells = <0>;
166 			compatible = "snps,designware-i2c";
171 			#address-cells = <1>;
172 			#size-cells = <0>;
177 			compatible = "snps,designware-i2c";
182 			#address-cells = <1>;
183 			#size-cells = <0>;
188 			compatible = "snps,designware-i2c";
193 			#address-cells = <1>;
194 			#size-cells = <0>;
199 			compatible = "arm,cryptocell-712-ree";