Lines Matching +full:cpu +full:- +full:capacity
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6002", "apple,arm-platform";
22 #address-cells = <2>;
23 #size-cells = <2>;
26 cpu-map {
29 cpu = <&cpu_e10>;
32 cpu = <&cpu_e11>;
38 cpu = <&cpu_p20>;
41 cpu = <&cpu_p21>;
44 cpu = <&cpu_p22>;
47 cpu = <&cpu_p23>;
53 cpu = <&cpu_p30>;
56 cpu = <&cpu_p31>;
59 cpu = <&cpu_p32>;
62 cpu = <&cpu_p33>;
67 cpu_e10: cpu@800 {
69 device_type = "cpu";
71 enable-method = "spin-table";
72 cpu-release-addr = <0 0>; /* To be filled by loader */
73 next-level-cache = <&l2_cache_3>;
74 i-cache-size = <0x20000>;
75 d-cache-size = <0x10000>;
76 operating-points-v2 = <&icestorm_opp>;
77 capacity-dmips-mhz = <714>;
78 performance-domains = <&cpufreq_e_die1>;
81 cpu_e11: cpu@801 {
83 device_type = "cpu";
85 enable-method = "spin-table";
86 cpu-release-addr = <0 0>; /* To be filled by loader */
87 next-level-cache = <&l2_cache_3>;
88 i-cache-size = <0x20000>;
89 d-cache-size = <0x10000>;
90 operating-points-v2 = <&icestorm_opp>;
91 capacity-dmips-mhz = <714>;
92 performance-domains = <&cpufreq_e_die1>;
95 cpu_p20: cpu@10900 {
97 device_type = "cpu";
99 enable-method = "spin-table";
100 cpu-release-addr = <0 0>; /* To be filled by loader */
101 next-level-cache = <&l2_cache_4>;
102 i-cache-size = <0x30000>;
103 d-cache-size = <0x20000>;
104 operating-points-v2 = <&firestorm_opp>;
105 capacity-dmips-mhz = <1024>;
106 performance-domains = <&cpufreq_p0_die1>;
109 cpu_p21: cpu@10901 {
111 device_type = "cpu";
113 enable-method = "spin-table";
114 cpu-release-addr = <0 0>; /* To be filled by loader */
115 next-level-cache = <&l2_cache_4>;
116 i-cache-size = <0x30000>;
117 d-cache-size = <0x20000>;
118 operating-points-v2 = <&firestorm_opp>;
119 capacity-dmips-mhz = <1024>;
120 performance-domains = <&cpufreq_p0_die1>;
123 cpu_p22: cpu@10902 {
125 device_type = "cpu";
127 enable-method = "spin-table";
128 cpu-release-addr = <0 0>; /* To be filled by loader */
129 next-level-cache = <&l2_cache_4>;
130 i-cache-size = <0x30000>;
131 d-cache-size = <0x20000>;
132 operating-points-v2 = <&firestorm_opp>;
133 capacity-dmips-mhz = <1024>;
134 performance-domains = <&cpufreq_p0_die1>;
137 cpu_p23: cpu@10903 {
139 device_type = "cpu";
141 enable-method = "spin-table";
142 cpu-release-addr = <0 0>; /* To be filled by loader */
143 next-level-cache = <&l2_cache_4>;
144 i-cache-size = <0x30000>;
145 d-cache-size = <0x20000>;
146 operating-points-v2 = <&firestorm_opp>;
147 capacity-dmips-mhz = <1024>;
148 performance-domains = <&cpufreq_p0_die1>;
151 cpu_p30: cpu@10a00 {
153 device_type = "cpu";
155 enable-method = "spin-table";
156 cpu-release-addr = <0 0>; /* To be filled by loader */
157 next-level-cache = <&l2_cache_5>;
158 i-cache-size = <0x30000>;
159 d-cache-size = <0x20000>;
160 operating-points-v2 = <&firestorm_opp>;
161 capacity-dmips-mhz = <1024>;
162 performance-domains = <&cpufreq_p1_die1>;
165 cpu_p31: cpu@10a01 {
167 device_type = "cpu";
169 enable-method = "spin-table";
170 cpu-release-addr = <0 0>; /* To be filled by loader */
171 next-level-cache = <&l2_cache_5>;
172 i-cache-size = <0x30000>;
173 d-cache-size = <0x20000>;
174 operating-points-v2 = <&firestorm_opp>;
175 capacity-dmips-mhz = <1024>;
176 performance-domains = <&cpufreq_p1_die1>;
179 cpu_p32: cpu@10a02 {
181 device_type = "cpu";
183 enable-method = "spin-table";
184 cpu-release-addr = <0 0>; /* To be filled by loader */
185 next-level-cache = <&l2_cache_5>;
186 i-cache-size = <0x30000>;
187 d-cache-size = <0x20000>;
188 operating-points-v2 = <&firestorm_opp>;
189 capacity-dmips-mhz = <1024>;
190 performance-domains = <&cpufreq_p1_die1>;
193 cpu_p33: cpu@10a03 {
195 device_type = "cpu";
197 enable-method = "spin-table";
198 cpu-release-addr = <0 0>; /* To be filled by loader */
199 next-level-cache = <&l2_cache_5>;
200 i-cache-size = <0x30000>;
201 d-cache-size = <0x20000>;
202 operating-points-v2 = <&firestorm_opp>;
203 capacity-dmips-mhz = <1024>;
204 performance-domains = <&cpufreq_p1_die1>;
207 l2_cache_3: l2-cache-3 {
209 cache-level = <2>;
210 cache-unified;
211 cache-size = <0x400000>;
214 l2_cache_4: l2-cache-4 {
216 cache-level = <2>;
217 cache-unified;
218 cache-size = <0xc00000>;
221 l2_cache_5: l2-cache-5 {
223 cache-level = <2>;
224 cache-unified;
225 cache-size = <0xc00000>;
230 compatible = "simple-bus";
231 #address-cells = <2>;
232 #size-cells = <2>;
236 nonposted-mmio;
242 compatible = "simple-bus";
243 #address-cells = <2>;
244 #size-cells = <2>;
247 nonposted-mmio;
257 #include "t600x-die0.dtsi"
258 #include "t600x-dieX.dtsi"
261 #include "t600x-pmgr.dtsi"
262 #include "t600x-gpio-pins.dtsi"
271 #include "t600x-dieX.dtsi"
272 #include "t600x-nvme.dtsi"
275 #include "t600x-pmgr.dtsi"
282 e-core-pmu-affinity {
283 apple,fiq-index = <AIC_CPU_PMU_E>;
288 p-core-pmu-affinity {
289 apple,fiq-index = <AIC_CPU_PMU_P>;
300 power-domains = <&ps_afr>, <&ps_afr_die1>;