Lines Matching +full:in +full:- +full:and +full:- +full:around
1 # SPDX-License-Identifier: GPL-2.0-only
279 ARM 64-bit (AArch64) Linux support.
287 # required due to use of the -Zfixed-x18 flag.
290 # -Zsanitizer=shadow-call-stack flag.
300 depends on $(cc-option,-fpatchable-function-entry=2)
326 # VA_BITS - PAGE_SHIFT - 3
404 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
409 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
412 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
445 …bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and …
448 This option adds an alternative code sequence to work around Ampere
449 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne.
451 The affected design reports FEAT_HAFDBS as not implemented in
459 at stage-2.
467 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
471 This option adds an alternative code sequence to work around ARM
472 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
473 AXI master interface and an L2 cache.
475 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
476 and is unable to accept a certain write via this interface, it will
477 not progress on read data presented on the read data channel and the
481 data cache clean-and-invalidate.
489 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
493 This option adds an alternative code sequence to work around ARM
494 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
495 master interface and an L2 cache.
503 data cache clean-and-invalidate.
511 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
515 This option adds an alternative code sequence to work around ARM
516 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
519 If a Cortex-A53 processor is executing a store or prefetch for
520 write instruction at the same time as a processor in another
526 data cache clean-and-invalidate.
534 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
538 This option adds an alternative code sequence to work around ARM
539 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
542 If the processor is executing a load and store exclusive sequence at
543 the same time as a processor in another cluster is executing a cache
548 data cache clean-and-invalidate.
556 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
559 This option adds an alternative code sequence to work around ARM
560 erratum 832075 on Cortex-A57 parts up to r1p2.
562 Affected Cortex-A57 parts might deadlock when exclusive load/store
563 instructions to Write-Back memory are mixed with Device loads.
565 The workaround is to promote device loads to use Load-Acquire
574 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
577 This option adds an alternative code sequence to work around ARM
578 erratum 834220 on Cortex-A57 parts up to r1p2.
580 Affected Cortex-A57 parts might report a Stage 2 translation
583 alignment fault at Stage 1 and a translation fault at Stage 2.
594 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
598 This option removes the AES hwcap for aarch32 user-space to
599 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
610 bool "Cortex-A53: 845719: a load might read incorrect data"
614 This option adds an alternative code sequence to work around ARM
615 erratum 845719 on Cortex-A53 parts up to r0p4.
617 When running a compat (AArch32) userspace on an affected Cortex-A53
623 return to a 32-bit task.
631 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
634 This option links the kernel with '--fix-cortex-a53-843419' and
637 Cortex-A53 parts up to r0p4.
642 def_bool $(ld-option,--fix-cortex-a53-843419)
645 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
648 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
650 Affected Cortex-A55 cores (all revisions) could cause incorrect
652 without a break-before-make. The workaround is to disable the usage
659 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
663 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
664 errata 1188873 and 1418040.
666 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
676 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
680 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
682 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
689 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
693 This option adds work arounds for ARM Cortex-A57 erratum 1319537
694 and A72 erratum 1319367
696 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
702 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
706 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
708 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
718 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
721 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
723 Under very rare circumstances, affected Cortex-A55 CPUs
724 may not handle a race between a break-before-make sequence on one
725 CPU, and another CPU accessing the same page. This could allow a
728 Work around this by adding the affected CPUs to the list that needs
734 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
737 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
739 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
743 break-before-make sequence, then under very rare circumstances
751 bool "Cortex-A76: Software Step might prevent interrupt recognition"
754 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
756 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
758 subsequent interrupts when software stepping is disabled in the
759 exception handler of the system call and either kernel debugging
760 is enabled or VHE is in use.
762 Work around the erratum by triggering a dummy step exception
764 in a VHE configuration of the kernel.
769 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
771 This option adds a workaround for ARM Neoverse-N1 erratum
774 Affected Neoverse-N1 cores could execute a stale instruction when
779 forces user-space to perform cache maintenance.
784 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
787 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
789 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
790 of a store-exclusive or read of PAR_EL1 and a load with device or
791 non-cacheable memory attributes. The workaround depends on a firmware
797 Work around the issue by inserting DMB SY barriers around PAR_EL1
798 register reads and warning KVM users. The DMB barrier is sufficient
807 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
810 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
811 Affected Cortex-A510 might not respect the ordering rules for
818 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
821 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
822 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
830 previous guest entry, and can be restored from the in-memory copy.
835 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
838 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
839 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
840 BFMMLA or VMMLA instructions in rare circumstances when a pair of
843 user-space should not be using these instructions.
848 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
853 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
855 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
856 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
859 Work around the issue by always making sure we move the TRBPTR_EL1 by
860 256 bytes before enabling the buffer and filling the first 256 bytes of
866 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
871 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
873 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
874 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
877 Work around the issue by always making sure we move the TRBPTR_EL1 by
878 256 bytes before enabling the buffer and filling the first 256 bytes of
887 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
891 Enable workaround for ARM Cortex-A710 erratum 2054223
894 the PE is in trace prohibited state. This will cause losing a few bytes
902 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
906 Enable workaround for ARM Neoverse-N2 erratum 2067961
909 the PE is in trace prohibited state. This will cause losing a few bytes
920 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
925 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
927 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
930 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
932 Work around this in the driver by always making sure that there is a
938 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
943 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
945 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
948 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
950 Work around this in the driver by always making sure that there is a
956 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
959 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
961 Under very rare circumstances, affected Cortex-A510 CPUs
962 may not handle a race between a break-before-make sequence on one
963 CPU, and another CPU accessing the same page. This could allow a
966 Work around this by adding the affected CPUs to the list that needs
972 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
976 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
978 Affected Cortex-A510 core might fail to write into system registers after the
981 and TRBTRG_EL1 will be ignored and will not be effected.
983 Work around this in the driver by executing TSB CSYNC and DSB after collection
984 is stopped and before performing a system register write to one of the affected
990 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
994 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
996 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1000 execution changes from a context, in which trace is prohibited to one where it
1001 isn't, or vice versa. In these mentioned conditions, the view of whether trace
1002 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
1005 Work around this in the driver by preventing an inconsistent view of whether the
1013 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1017 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1019 Affected Cortex-A510 core might cause trace data corruption, when being written
1020 into the memory. Effectively TRBE is broken and hence cannot be used to capture
1023 Work around this problem in the driver by just preventing TRBE initialization on
1031 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1035 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1038 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1041 Work around this problem by returning 0 when reading the affected counter in
1042 key locations that results in disabling all users of this counter. This effect
1048 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1051 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1053 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1054 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1057 Only user-space does executable to non-executable permission transition via
1058 mprotect() system call. Workaround the problem by doing a break-before-make
1067 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1071 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1073 On an affected Cortex-A520 core, a speculatively executed unprivileged
1076 Work around this problem by executing a TLBI before returning to EL0.
1081 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1085 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1087 On an affected Cortex-A510 core, a speculatively executed unprivileged
1090 Work around this problem by executing a TLBI before returning to EL0.
1095 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1100 * ARM Cortex-A76 erratum 3324349
1101 * ARM Cortex-A77 erratum 3324348
1102 * ARM Cortex-A78 erratum 3324344
1103 * ARM Cortex-A78C erratum 3324346
1104 * ARM Cortex-A78C erratum 3324347
1105 * ARM Cortex-A710 erratam 3324338
1106 * ARM Cortex-A715 errartum 3456084
1107 * ARM Cortex-A720 erratum 3456091
1108 * ARM Cortex-A725 erratum 3456106
1109 * ARM Cortex-X1 erratum 3324344
1110 * ARM Cortex-X1C erratum 3324346
1111 * ARM Cortex-X2 erratum 3324338
1112 * ARM Cortex-X3 erratum 3324335
1113 * ARM Cortex-X4 erratum 3194386
1114 * ARM Cortex-X925 erratum 3324334
1115 * ARM Neoverse-N1 erratum 3324349
1117 * ARM Neoverse-N3 erratum 3456111
1118 * ARM Neoverse-V1 erratum 3324341
1120 * ARM Neoverse-V3 erratum 3312417
1126 Work around this problem by placing a Speculation Barrier (SB) or
1128 SSBS. The presence of the SSBS special-purpose register is hidden
1129 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace
1138 Enable workaround for errata 22375 and 24313.
1140 This implements two gicv3-its errata workarounds for ThunderX. Both
1146 The fixes are in ITS initialization and basically ignore memory access
1147 type and table size provided by the TYPER and BASER registers.
1156 ITS SYNC command hang for cross node io and collections/cpu mapping.
1161 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1166 (access to icc_iar1_el1 is not sync'ed before and after).
1169 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1180 contains data for a non-current ASID. The fix is to
1186 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1190 1.2, and T83 Pass 1.0, KVM guest execution may disable
1191 interrupts in host. Trapping both GICv3 group-0 and group-1
1197 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1201 TTBR update and the corresponding context synchronizing operation can
1202 cause a spurious Data Abort to be delivered to any hardware thread in
1205 Work around the issue by avoiding the problematic code sequence and
1208 instruction and ensures context synchronization by virtue of the
1214 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1217 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1218 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1222 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1223 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1224 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1225 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1227 The workaround is to ensure these bits are clear in TCR_ELx.
1228 The workaround only affects the Fujitsu-A64FX.
1237 when issued ITS commands such as VMOVP and VMAPP, and requires
1238 a 128kB offset to be applied to the target address in this commands.
1246 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches
1257 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1258 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1259 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1260 then only for entries in the walk cache, since the leaf translation
1261 is unchanged. Work around the erratum by invalidating the walk cache
1299 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1309 The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI
1318 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1325 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1329 MSI doorbell writes with non-zero values for the device ID.
1360 allowing only two levels of page tables and faster TLB
1361 look-up. AArch32 emulation requires applications compiled
1372 a combination of page size and virtual address space size.
1375 bool "36-bit" if EXPERT
1379 bool "39-bit"
1383 bool "42-bit"
1387 bool "47-bit"
1391 bool "48-bit"
1394 bool "52-bit"
1396 Enable 52-bit virtual addressing for userspace when explicitly
1397 requested via a hint to mmap(). The kernel will also use 52-bit
1399 this feature is available, otherwise it reverts to 48-bit).
1401 NOTE: Enabling 52-bit virtual addressing in conjunction with
1402 ARMv8.3 Pointer Authentication will result in the PAC being
1404 impact on its susceptibility to brute-force attacks.
1406 If unsure, select 48-bit virtual addressing instead.
1411 bool "Force 52-bit virtual addresses for userspace"
1414 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1415 to maintain compatibility with older software by providing 48-bit VAs
1418 This configuration option disables the 48-bit compatibility logic, and
1419 forces all userspace addresses to be 52-bit on HW that supports it. One
1440 bool "48-bit"
1444 bool "52-bit"
1447 Enable support for a 52-bit physical address space, introduced as
1448 part of the ARMv8.2-LPA extension.
1451 do not support ARMv8.2-LPA, but with some added memory overhead (and
1470 applications will need to be compiled and linked for the endianness
1474 bool "Build big-endian kernel"
1475 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1478 Say Y if you plan on running a kernel with a big-endian userspace.
1481 bool "Build little-endian kernel"
1483 Say Y if you plan on running a kernel with a little-endian userspace.
1489 bool "Multi-core scheduler support"
1491 Multi-core scheduler support improves the CPU scheduler's decision
1492 making when dealing with multi-core CPU chips at a cost of slightly
1493 increased overhead in some places. If unsure say N here.
1501 by sharing mid-level caches, last-level cache tags or internal
1508 MultiThreading at a cost of slightly increased overhead in some
1512 int "Maximum number of CPUs (2-4096)"
1517 bool "Support for hot-pluggable CPUs"
1520 Say Y here to experiment with turning CPUs off and on. CPUs
1525 bool "NUMA Memory Allocation and Scheduler Support"
1533 Enable NUMA (Non-Uniform Memory Access) support.
1536 local memory of the CPU and add some more
1561 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1575 accounting. Time spent executing other tasks in parallel with
1579 If in doubt, say N here.
1624 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1630 # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1633 # ----+-------------------+--------------+----------------------+-------------------------+
1644 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
1658 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT
1661 Speculation attacks against some high-performance processors can
1662 be used to bypass MMU permission checks and leak kernel data to
1664 when running in userspace, mapping it back in on exception entry
1665 via a trampoline page in the vector table.
1673 Speculation attacks against some high-performance processors can
1675 When taking an exception from user-space, a sequence of branches
1682 Apply read-only attributes of VM areas to the linear alias of
1683 the backing pages as well. This prevents code or read-only data
1686 be turned off at runtime by passing rodata=[off|on] (and turned on
1690 which may adversely affect performance in some cases.
1698 user-space memory directly by pointing TTBR0_EL1 to a reserved
1699 zeroed area and reserved ASID. The user access routines
1706 When this option is enabled, user applications can opt in to a
1709 Documentation/arch/arm64/tagged-address-abi.rst.
1712 bool "Kernel support for 32-bit EL0"
1718 This option enables support for a 32-bit EL0 running under a 64-bit
1719 kernel at EL1. AArch32-specific components such as system calls,
1720 the user helper functions, VFP support and the ptrace interface are
1727 If you want to execute 32-bit userspace applications, say Y.
1732 bool "Enable kuser helpers page for 32-bit applications"
1735 Warning: disabling this option may break 32-bit user programs.
1738 helper code to userspace in read only form at a fixed location
1749 If all of the binaries and libraries which run on your platform
1750 are built specifically for your platform, and make no use of
1752 such exploits. However, in that case, if a binary or library
1759 bool "Enable vDSO for 32-bit applications"
1765 Place in the process address space of 32-bit applications an
1767 and clock_gettime.
1769 You must have a 32-bit build of glibc 2.22 or later for programs
1773 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1777 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1778 otherwise with '-marm'.
1781 bool "Fix up misaligned multi-word loads and stores in user space"
1788 that have been deprecated or obsoleted in the architecture.
1806 In some older versions of glibc [<=2.8] SWP is used during futex
1823 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1824 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1825 strongly recommended to use the ISB, DSB, and DMB
1839 The SETEND instruction alters the data-endianness of the
1840 AArch32 EL0, and is deprecated in ARMv8.
1847 for this feature to be enabled. If a new CPU - which doesn't support mixed
1848 endian - is hotplugged in after this feature has been enabled, there could
1849 be unexpected results in the applications.
1859 bool "Support for hardware updates of the Access and Dirty page flags"
1863 hardware updates of the access and dirty information in page
1864 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1867 Similarly, writes to read-only pages with the DBM bit set will
1868 clear the read-only bit (AP[2]) instead of raising a
1872 to work on pre-ARMv8.1 hardware and the performance impact is
1880 prevents the kernel or hypervisor from accessing user-space (EL0)
1886 The feature is detected at runtime, and will remain as a 'nop'
1890 def_bool $(as-instr,.arch_extension lse)
1902 atomic instructions that are designed specifically to scale in
1905 Say Y here to make use of these instructions for the in-kernel
1907 not support these instructions and requires the kernel to be
1908 built with binutils >= 2.25 in order for the new instructions
1916 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1919 def_bool $(as-instr,.arch armv8.2-a+sha3)
1929 The feature is detected at runtime, and the kernel will use DC CVAC
1937 CPUs that support the Reliability, Availability and Serviceability
1938 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1939 errors, classify them and report them to software.
1942 barriers to determine if faults are pending and read the
1946 and access the new registers if the system supports the extension.
1954 be shared between different PEs in the same inner shareable
1956 caching of such entries in the TLB.
1959 at runtime, and does not affect PEs that do not implement
1971 instructions for signing and authenticating pointers against secret
1973 and other attacks.
1978 context-switched along with the process.
1980 The feature is detected at runtime. If the feature is not present in
1986 address auth and the late CPU has then the late CPU will still boot
2001 If the compiler supports the -mbranch-protection or
2002 -msign-return-address flag (e.g. GCC 7 or later), then this option
2004 protection. In this case, and if the target hardware is known to
2013 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
2017 def_bool $(cc-option,-msign-return-address=all)
2020 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
2023 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
2026 def_bool $(as-instr,.arch_extension rcpc)
2044 extension. The required support is present in:
2045 * Version 1.5 and later of the ARM Trusted Firmware
2056 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
2063 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2066 The feature introduces new assembly instructions, and they were
2074 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2111 and enable enforcement of this for kernel code. When this option
2112 is enabled and the system supports BTI all kernel code including
2117 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2124 that EL0 accesses made via TTBR1 always fault in constant time,
2126 with lower overhead and without disrupting legitimate access to
2132 # Initial support for MTE went in binutils 2.32.0, checked with
2133 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2135 # is only supported in the newer 2.32.x and 2.33 binutils
2137 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2145 # Required for tag checking in the uaccess routines
2153 architectural support for run-time, always-on detection of
2155 to eliminate vulnerabilities arising from memory-unsafe
2163 not be allowed a late bring-up.
2166 explicitly opt in. The mechanism for the userspace is
2167 described in:
2169 Documentation/arch/arm64/memory-tagging-extension.rst.
2181 Access Never to be used with Execute-only mappings.
2183 The feature is detected at runtime, and will remain disabled
2188 def_bool $(as-instr,.arch_extension mops)
2200 enforcing page-based protections, but without requiring modification
2203 For details, see Documentation/core-api/protection-keys.rst
2218 memory access will update the Access Flag in each Table descriptor
2219 which is accessed during the translation table walk and for which
2223 The feature will only be enabled if all the CPUs in the system
2241 stored in the GCS, and may also be used to efficiently obtain
2244 The feature is detected at runtime, and will remain disabled
2254 execution state which complements and extends the SIMD functionality
2255 of the base architecture to support much larger vectors and to enable
2265 is present in:
2267 * version 1.5 and later of the ARM Trusted Firmware
2269 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2274 If you need the kernel to boot on SVE-capable hardware with broken
2277 booting the kernel. If unsure and you are not observing these
2293 bool "Support for NMI-like interrupts"
2296 Adds support for mimicking Non-Maskable Interrupts through the use of
2339 random u64 value in /chosen/kaslr-seed at kernel entry.
2343 to the kernel proper. In addition, it will randomise the physical
2356 but it does imply that function calls between modules and the core
2357 kernel will need to be resolved via veneers in the module PLT.
2361 core kernel, so branch relocations are almost always in range unless
2362 the region is exhausted. In this particular case of region
2366 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2374 …# needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea…
2387 bit, for any mappings that meet the size and alignment requirements.
2388 This reduces TLB pressure and improves performance.
2400 protocol even if the corresponding data is present in the ACPI
2407 Provide a set of default command-line options at build time by
2422 Uses the command-line options passed by the boot loader. If
2424 string provided in CMDLINE will be used.
2432 command-line options your boot loader passes to the kernel.
2454 by UEFI firmware (such as non-volatile variables, realtime
2455 clock, and platform reset). A UEFI stub is also provided to
2466 "make zinstall" first, and verifying that everything is fine
2467 in your environment before making "make install" do this for
2479 continue to boot on existing non-UEFI platforms.