Lines Matching +full:default +full:- +full:on
1 # SPDX-License-Identifier: GPL-2.0-only
279 ARM 64-bit (AArch64) Linux support.
283 depends on CPU_LITTLE_ENDIAN
284 # Shadow call stack is only supported on certain rustc versions.
287 # required due to use of the -Zfixed-x18 flag.
290 # -Zsanitizer=shadow-call-stack flag.
291 …depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATC…
296 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
300 depends on $(cc-option,-fpatchable-function-entry=2)
310 default 5 if PAGE_SIZE_64KB
311 default 7 if PAGE_SIZE_16KB
312 default 4
316 default 5 if PAGE_SIZE_64KB
317 default 5 if PAGE_SIZE_16KB
318 default 4
321 default 14 if PAGE_SIZE_64KB
322 default 16 if PAGE_SIZE_16KB
323 default 18
326 # VA_BITS - PAGE_SHIFT - 3
328 default 19 if ARM64_VA_BITS=36
329 default 24 if ARM64_VA_BITS=39
330 default 27 if ARM64_VA_BITS=42
331 default 30 if ARM64_VA_BITS=47
332 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
333 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
334 default 33 if ARM64_VA_BITS=48
335 default 14 if ARM64_64K_PAGES
336 default 16 if ARM64_16K_PAGES
337 default 18
340 default 7 if ARM64_64K_PAGES
341 default 9 if ARM64_16K_PAGES
342 default 11
345 default 16
355 default 0xdead000000000000
362 depends on BUG
366 depends on GENERIC_BUG
388 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
389 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
390 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
391 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
392 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
393 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
394 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
395 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52
404 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
409 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
410 default y if CC_IS_CLANG
414 default y if CC_IS_GCC && (GCC_VERSION >= 110100)
415 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)
416 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000)
417 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000)
418 default n
422 depends on KASAN_GENERIC || KASAN_SW_TAGS
423 …default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KAS…
424 …default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_…
425 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
426 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
427 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
428 …default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASA…
429 …default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_S…
430 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
431 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
432 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
433 default 0xffffffffffffffff
446 default y
449 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne.
459 at stage-2.
467 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
468 default y
472 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
475 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
477 not progress on read data presented on the read data channel and the
481 data cache clean-and-invalidate.
483 as it depends on the alternative framework, which will only patch
489 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
490 default y
494 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
499 on the AMBA 5 CHI interface, which can cause data corruption if the
503 data cache clean-and-invalidate.
505 as it depends on the alternative framework, which will only patch
511 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
512 default y
516 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
519 If a Cortex-A53 processor is executing a store or prefetch for
526 data cache clean-and-invalidate.
528 workaround, as it depends on the alternative framework, which will
534 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
535 default y
539 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
548 data cache clean-and-invalidate.
550 as it depends on the alternative framework, which will only patch
556 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
557 default y
560 erratum 832075 on Cortex-A57 parts up to r1p2.
562 Affected Cortex-A57 parts might deadlock when exclusive load/store
563 instructions to Write-Back memory are mixed with Device loads.
565 The workaround is to promote device loads to use Load-Acquire
568 as it depends on the alternative framework, which will only patch
574 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
575 depends on KVM
578 erratum 834220 on Cortex-A57 parts up to r1p2.
580 Affected Cortex-A57 parts might report a Stage 2 translation
588 as it depends on the alternative framework, which will only patch
594 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
595 depends on COMPAT
596 default y
598 This option removes the AES hwcap for aarch32 user-space to
599 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
610 bool "Cortex-A53: 845719: a load might read incorrect data"
611 depends on COMPAT
612 default y
615 erratum 845719 on Cortex-A53 parts up to r0p4.
617 When running a compat (AArch32) userspace on an affected Cortex-A53
622 The workaround is to write the contextidr_el1 register on exception
623 return to a 32-bit task.
625 as it depends on the alternative framework, which will only patch
631 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
632 default y
634 This option links the kernel with '--fix-cortex-a53-843419' and
636 cause subsequent memory accesses to use an incorrect address on
637 Cortex-A53 parts up to r0p4.
642 def_bool $(ld-option,--fix-cortex-a53-843419)
645 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
646 default y
648 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
650 Affected Cortex-A55 cores (all revisions) could cause incorrect
652 without a break-before-make. The workaround is to disable the usage
653 of hardware DBM locally on the affected cores. CPUs not affected by
659 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
660 default y
661 depends on COMPAT
663 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
666 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
676 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
677 default y
680 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
682 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
689 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
690 default y
693 This option adds work arounds for ARM Cortex-A57 erratum 1319537
696 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
702 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
703 default y
706 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
708 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
718 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
721 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
723 Under very rare circumstances, affected Cortex-A55 CPUs
724 may not handle a race between a break-before-make sequence on one
734 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
737 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
739 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
743 break-before-make sequence, then under very rare circumstances
751 bool "Cortex-A76: Software Step might prevent interrupt recognition"
752 default y
754 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
756 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
769 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
771 This option adds a workaround for ARM Neoverse-N1 erratum
774 Affected Neoverse-N1 cores could execute a stale instruction when
775 modified by another CPU. The workaround depends on a firmware
779 forces user-space to perform cache maintenance.
784 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
785 default y
787 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
789 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
790 of a store-exclusive or read of PAR_EL1 and a load with device or
791 non-cacheable memory attributes. The workaround depends on a firmware
807 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
808 default y
810 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
811 Affected Cortex-A510 might not respect the ordering rules for
813 is to not enable the feature on affected CPUs.
818 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
819 default y
821 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
822 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
830 previous guest entry, and can be restored from the in-memory copy.
835 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
836 default y
838 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
839 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
843 user-space should not be using these instructions.
848 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
849 default y
850 depends on CORESIGHT_TRBE
853 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
855 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
866 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
867 default y
868 depends on CORESIGHT_TRBE
871 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
873 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
887 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
888 default y
891 Enable workaround for ARM Cortex-A710 erratum 2054223
893 Affected cores may fail to flush the trace data on a TSB instruction, when
897 Workaround is to issue two TSB consecutively on affected cores.
902 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
903 default y
906 Enable workaround for ARM Neoverse-N2 erratum 2067961
908 Affected cores may fail to flush the trace data on a TSB instruction, when
912 Workaround is to issue two TSB consecutively on affected cores.
920 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
921 depends on CORESIGHT_TRBE
922 default y
925 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
927 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
938 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
939 depends on CORESIGHT_TRBE
940 default y
943 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
945 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
956 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
959 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
961 Under very rare circumstances, affected Cortex-A510 CPUs
962 may not handle a race between a break-before-make sequence on one
972 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
973 depends on CORESIGHT_TRBE
974 default y
976 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
978 Affected Cortex-A510 core might fail to write into system registers after the
990 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
991 depends on CORESIGHT_TRBE
992 default y
994 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
996 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1006 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
1013 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1014 depends on CORESIGHT_TRBE
1015 default y
1017 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1019 Affected Cortex-A510 core might cause trace data corruption, when being written
1023 Work around this problem in the driver by just preventing TRBE initialization on
1025 on such implementations. This will cover the kernel for any firmware that doesn't
1031 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1032 depends on ARM64_AMU_EXTN
1033 default y
1035 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1038 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1048 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1049 default y
1051 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1053 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1054 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1057 Only user-space does executable to non-executable permission transition via
1058 mprotect() system call. Workaround the problem by doing a break-before-make
1067 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1069 default y
1071 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1073 On an affected Cortex-A520 core, a speculatively executed unprivileged
1081 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1083 default y
1085 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1087 On an affected Cortex-A510 core, a speculatively executed unprivileged
1095 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1096 default y
1100 * ARM Cortex-A76 erratum 3324349
1101 * ARM Cortex-A77 erratum 3324348
1102 * ARM Cortex-A78 erratum 3324344
1103 * ARM Cortex-A78C erratum 3324346
1104 * ARM Cortex-A78C erratum 3324347
1105 * ARM Cortex-A710 erratam 3324338
1106 * ARM Cortex-A715 errartum 3456084
1107 * ARM Cortex-A720 erratum 3456091
1108 * ARM Cortex-A725 erratum 3456106
1109 * ARM Cortex-X1 erratum 3324344
1110 * ARM Cortex-X1C erratum 3324346
1111 * ARM Cortex-X2 erratum 3324338
1112 * ARM Cortex-X3 erratum 3324335
1113 * ARM Cortex-X4 erratum 3194386
1114 * ARM Cortex-X925 erratum 3324334
1115 * ARM Neoverse-N1 erratum 3324349
1117 * ARM Neoverse-N3 erratum 3456111
1118 * ARM Neoverse-V1 erratum 3324341
1120 * ARM Neoverse-V3 erratum 3312417
1122 On affected cores "MSR SSBS, #0" instructions may not affect
1128 SSBS. The presence of the SSBS special-purpose register is hidden
1136 default y
1140 This implements two gicv3-its errata workarounds for ThunderX. Both
1152 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1153 depends on NUMA
1154 default y
1162 default y
1168 It also suffers from erratum 38545 (also present on Marvell's
1176 default y
1178 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1180 contains data for a non-current ASID. The fix is to
1187 default y
1189 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1191 interrupts in host. Trapping both GICv3 group-0 and group-1
1198 default y
1200 On Cavium ThunderX2, a load, store or prefetch instruction between a
1214 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1215 default y
1217 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1218 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1222 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1223 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1224 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1225 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1228 The workaround only affects the Fujitsu-A64FX.
1234 default y
1244 default y
1255 default y
1257 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1266 default y
1269 On Falkor v1, the CPU may prematurely complete a DSB following a
1277 default y
1279 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1287 default y
1296 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1297 default y
1299 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1301 on standard ARM cores.
1307 default y
1316 default y
1318 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1325 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1326 default y
1329 MSI doorbell writes with non-zero values for the device ID.
1337 default ARM64_4K_PAGES
1359 This feature enables 64KB pages support (4KB by default)
1361 look-up. AArch32 emulation requires applications compiled
1368 default ARM64_VA_BITS_52
1375 bool "36-bit" if EXPERT
1376 depends on PAGE_SIZE_16KB
1379 bool "39-bit"
1380 depends on PAGE_SIZE_4KB
1383 bool "42-bit"
1384 depends on PAGE_SIZE_64KB
1387 bool "47-bit"
1388 depends on PAGE_SIZE_16KB
1391 bool "48-bit"
1394 bool "52-bit"
1396 Enable 52-bit virtual addressing for userspace when explicitly
1397 requested via a hint to mmap(). The kernel will also use 52-bit
1399 this feature is available, otherwise it reverts to 48-bit).
1401 NOTE: Enabling 52-bit virtual addressing in conjunction with
1404 impact on its susceptibility to brute-force attacks.
1406 If unsure, select 48-bit virtual addressing instead.
1411 bool "Force 52-bit virtual addresses for userspace"
1412 depends on ARM64_VA_BITS_52 && EXPERT
1414 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1415 to maintain compatibility with older software by providing 48-bit VAs
1418 This configuration option disables the 48-bit compatibility logic, and
1419 forces all userspace addresses to be 52-bit on HW that supports it. One
1425 default 36 if ARM64_VA_BITS_36
1426 default 39 if ARM64_VA_BITS_39
1427 default 42 if ARM64_VA_BITS_42
1428 default 47 if ARM64_VA_BITS_47
1429 default 48 if ARM64_VA_BITS_48
1430 default 52 if ARM64_VA_BITS_52
1434 default ARM64_PA_BITS_48
1440 bool "48-bit"
1441 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52
1444 bool "52-bit"
1445 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52
1447 Enable support for a 52-bit physical address space, introduced as
1448 part of the ARMv8.2-LPA extension.
1450 With this enabled, the kernel will also continue to work on CPUs that
1451 do not support ARMv8.2-LPA, but with some added memory overhead (and
1458 default 48 if ARM64_PA_BITS_48
1459 default 52 if ARM64_PA_BITS_52
1463 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES
1467 default CPU_LITTLE_ENDIAN
1474 bool "Build big-endian kernel"
1475 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1476 depends on AS_IS_GNU || AS_VERSION >= 150000
1478 Say Y if you plan on running a kernel with a big-endian userspace.
1481 bool "Build little-endian kernel"
1483 Say Y if you plan on running a kernel with a little-endian userspace.
1489 bool "Multi-core scheduler support"
1491 Multi-core scheduler support improves the CPU scheduler's decision
1492 making when dealing with multi-core CPU chips at a cost of slightly
1501 by sharing mid-level caches, last-level cache tags or internal
1512 int "Maximum number of CPUs (2-4096)"
1514 default "512"
1517 bool "Support for hot-pluggable CPUs"
1520 Say Y here to experiment with turning CPUs off and on. CPUs
1533 Enable NUMA (Non-Uniform Memory Access) support.
1535 The kernel will try to allocate memory used by a CPU on the
1542 default "4"
1543 depends on NUMA
1545 Specify the maximum number of NUMA Nodes available on the target
1557 depends on ARM_PMU
1561 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1589 depends on KEXEC_FILE
1612 depends on HIBERNATION || KEXEC_CORE
1616 depends on XEN
1619 bool "Xen guest support on ARM64"
1620 depends on ARM64 && OF
1624 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1630 # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1632 # | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER |
1633 # ----+-------------------+--------------+----------------------+-------------------------+
1639 default "13" if ARM64_64K_PAGES
1640 default "11" if ARM64_16K_PAGES
1641 default "10"
1647 overriding the default setting when ability to allocate very
1659 default y
1661 Speculation attacks against some high-performance processors can
1664 when running in userspace, mapping it back in on exception entry
1671 default y
1673 Speculation attacks against some high-performance processors can
1675 When taking an exception from user-space, a sequence of branches
1680 default y
1682 Apply read-only attributes of VM areas to the linear alias of
1683 the backing pages as well. This prevents code or read-only data
1686 be turned off at runtime by passing rodata=[off|on] (and turned on
1694 depends on !KCSAN
1698 user-space memory directly by pointing TTBR0_EL1 to a reserved
1704 default y
1709 Documentation/arch/arm64/tagged-address-abi.rst.
1712 bool "Kernel support for 32-bit EL0"
1713 depends on ARM64_4K_PAGES || EXPERT
1718 This option enables support for a 32-bit EL0 running under a 64-bit
1719 kernel at EL1. AArch32-specific components such as system calls,
1727 If you want to execute 32-bit userspace applications, say Y.
1732 bool "Enable kuser helpers page for 32-bit applications"
1733 default y
1735 Warning: disabling this option may break 32-bit user programs.
1740 the system. This permits binaries to be run on ARMv4 through
1749 If all of the binaries and libraries which run on your platform
1753 relying on those helpers is run, it will not function correctly.
1759 bool "Enable vDSO for 32-bit applications"
1760 depends on !CPU_BIG_ENDIAN
1761 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1763 default y
1765 Place in the process address space of 32-bit applications an
1769 You must have a 32-bit build of glibc 2.22 or later for programs
1773 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1774 depends on COMPAT_VDSO
1775 default y
1777 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1778 otherwise with '-marm'.
1781 bool "Fix up misaligned multi-word loads and stores in user space"
1785 depends on SYSCTL
1804 sysctl which is disabled by default.
1813 on an external transaction monitoring block called a global
1823 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1824 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1839 The SETEND instruction alters the data-endianness of the
1846 Note: All the cpus on the system must have mixed endian support at EL0
1847 for this feature to be enabled. If a new CPU - which doesn't support mixed
1848 endian - is hotplugged in after this feature has been enabled, there could
1860 default y
1864 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1867 Similarly, writes to read-only pages with the DBM bit set will
1868 clear the read-only bit (AP[2]) instead of raising a
1872 to work on pre-ARMv8.1 hardware and the performance impact is
1877 default y
1880 prevents the kernel or hypervisor from accessing user-space (EL0)
1890 def_bool $(as-instr,.arch_extension lse)
1894 default ARM64_USE_LSE_ATOMICS
1895 depends on AS_HAS_LSE_ATOMICS
1899 default y
1905 Say Y here to make use of these instructions for the in-kernel
1906 atomic routines. This incurs a small overhead on CPUs that do
1916 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1919 def_bool $(as-instr,.arch armv8.2-a+sha3)
1926 Say Y to enable support for the persistent memory API based on the
1935 default y
1941 On CPUs with these extensions system software can use additional
1947 Platform RAS features may additionally depend on firmware support.
1951 default y
1968 default y
1978 context-switched along with the process.
1984 If the feature is present on the boot CPU but not on a late CPU, then
1987 but with the feature disabled. On such a system, this option should
1992 default y
1993 depends on ARM64_PTR_AUTH
1994 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3
1997 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1998 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1999 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
2001 If the compiler supports the -mbranch-protection or
2002 -msign-return-address flag (e.g. GCC 7 or later), then this option
2013 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
2017 def_bool $(cc-option,-msign-return-address=all)
2020 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
2023 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
2026 def_bool $(as-instr,.arch_extension rcpc)
2034 default y
2040 To enable the use of this extension on CPUs that implement it, say Y.
2043 support when running on CPUs that present the activity monitors
2056 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
2060 default y
2061 depends on AS_HAS_ARMV8_4
2063 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2074 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2078 default y
2084 To make use of BTI on CPUs that support it, say Y.
2100 default y
2101 depends on ARM64_BTI
2102 depends on ARM64_PTR_AUTH_KERNEL
2103 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
2105 depends on !CC_IS_GCC || GCC_VERSION >= 100100
2107 depends on !CC_IS_GCC
2108 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
2117 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2121 default y
2133 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2137 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2141 default y
2142 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2143 depends on AS_HAS_ARMV8_5
2144 depends on AS_HAS_LSE_ATOMICS
2153 architectural support for run-time, always-on detection of
2155 to eliminate vulnerabilities arising from memory-unsafe
2163 not be allowed a late bring-up.
2169 Documentation/arch/arm64/memory-tagging-extension.rst.
2177 default y
2178 depends on ARM64_PAN
2181 Access Never to be used with Execute-only mappings.
2188 def_bool $(as-instr,.arch_extension mops)
2200 enforcing page-based protections, but without requiring modification
2203 For details, see Documentation/core-api/protection-keys.rst
2209 default 3
2213 depends on ARM64_HW_AFDBM
2214 default y
2232 default y
2235 depends on !UPROBES
2251 default y
2258 To enable use of this extension on CPUs that implement it, say Y.
2260 On CPUs that support the SVE2 extensions, this option will enable
2264 support when running on SVE capable hardware. The required support
2274 If you need the kernel to boot on SVE-capable hardware with broken
2282 default y
2283 depends on ARM64_SVE
2284 depends on BROKEN
2293 bool "Support for NMI-like interrupts"
2296 Adds support for mimicking Non-Maskable Interrupts through the use of
2320 default y
2336 relying on knowledge of the location of kernel internals.
2339 random u64 value in /chosen/kaslr-seed at kernel entry.
2350 depends on RANDOMIZE_BASE
2351 default y
2366 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2370 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2374 …# needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea…
2375 depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2376 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2377 depends on SHADOW_CALL_STACK
2383 depends on TRANSPARENT_HUGEPAGE
2384 default y
2396 depends on ACPI
2404 string "Default kernel command string"
2405 default ""
2407 Provide a set of default command-line options at build time by
2413 depends on CMDLINE != ""
2414 default CMDLINE_FROM_BOOTLOADER
2416 Choose how the kernel will handle the provided default kernel
2422 Uses the command-line options passed by the boot loader. If
2423 the boot loader doesn't provide any, the default kernel command
2427 bool "Always use the default kernel command string"
2429 Always use the default kernel command string, even if the boot
2432 command-line options your boot loader passes to the kernel.
2441 depends on OF && !CPU_BIG_ENDIAN
2442 depends on KERNEL_MODE_NEON
2451 default y
2454 by UEFI firmware (such as non-volatile variables, realtime
2457 is only useful on systems that have UEFI firmware.
2460 bool "Install compressed image by default"
2472 depends on EFI
2473 default y
2477 This option is only useful on systems that have UEFI firmware.
2479 continue to boot on existing non-UEFI platforms.
2489 depends on CPU_PM
2493 depends on HIBERNATION