Lines Matching +full:0 +full:xfffffff0
60 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
62 #define CLEAN_ADDR 0xfffe0000
70 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
76 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
92 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
94 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
117 mrc p15, 0, r1, c1, c0, 1
119 mcr p15, 0, r1, c1, c0, 1
127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
128 bic r0, r0, #0x1800 @ ...IZ...........
129 bic r0, r0, #0x0006 @ .............CA.
130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
150 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
151 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
152 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
153 bic r1, r1, #0x0086 @ ........B....CA.
154 bic r1, r1, #0x3900 @ ..VIZ..S........
157 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
158 bic r1, r1, #0x0001 @ ...............M
159 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
160 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
163 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
182 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
194 mov r0, #0
195 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
214 mov ip, #0
218 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
219 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
235 mov ip, #0
241 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
242 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
243 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
248 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
249 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
268 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
272 mov r0, #0
273 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
274 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
290 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
291 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
295 mov r0, #0
296 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
297 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
312 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
313 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
317 mov r0, #0
318 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
319 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
337 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
339 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
340 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
344 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
357 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
361 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
374 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
375 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
379 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
435 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
454 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
455 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
456 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
457 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
469 .long 0x00 @ L_PTE_MT_UNCACHED
474 .long 0x00 @ unused
477 .long 0x00 @ unused
479 .long 0x00 @ unused
481 .long 0x00 @ L_PTE_MT_DEV_NONSHARED
482 .long 0x00 @ unused
483 .long 0x00 @ unused
484 .long 0x00 @ unused
500 bic r2, r2, #0x0c
515 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
516 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
517 mrc p15, 0, r6, c13, c0, 0 @ PID
518 mrc p15, 0, r7, c3, c0, 0 @ domain ID
519 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
520 mrc p15, 0, r9, c1, c0, 0 @ control reg
528 mov ip, #0
529 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
530 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
531 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
532 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
533 mcr p15, 0, r6, c13, c0, 0 @ PID
534 mcr p15, 0, r7, c3, c0, 0 @ domain ID
535 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
536 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
544 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
545 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
546 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
549 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
553 mrc p15, 0, r0, c1, c0, 0 @ get control register
567 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
627 xscale_proc_info 80200_A0_A1, 0x69052000, 0xfffffffe, cpu_80200_name, \
629 xscale_proc_info 80200, 0x69052000, 0xfffffff0, cpu_80200_name
630 xscale_proc_info 80219, 0x69052e20, 0xffffffe0, cpu_80219_name
631 xscale_proc_info 8032x, 0x69052420, 0xfffff7e0, cpu_8032x_name
632 xscale_proc_info 8033x, 0x69054010, 0xfffffd30, cpu_8033x_name
633 xscale_proc_info pxa250, 0x69052100, 0xfffff7f0, cpu_pxa250_name
634 xscale_proc_info pxa210, 0x69052120, 0xfffff3f0, cpu_pxa210_name
635 xscale_proc_info ixp2400, 0x69054190, 0xfffffff0, cpu_ixp2400_name
636 xscale_proc_info ixp2800, 0x690541a0, 0xfffffff0, cpu_ixp2800_name
637 xscale_proc_info ixp42x, 0x690541c0, 0xffffffc0, cpu_ixp42x_name
638 xscale_proc_info ixp43x, 0x69054040, 0xfffffff0, cpu_ixp43x_name
639 xscale_proc_info ixp46x, 0x69054200, 0xffffff00, cpu_ixp46x_name
640 xscale_proc_info pxa255, 0x69052d00, 0xfffffff0, cpu_pxa255_name
641 xscale_proc_info pxa270, 0x69054110, 0xfffffff0, cpu_pxa270_name