Lines Matching +full:disable +full:- +full:mmu +full:- +full:reset

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  linux/arch/arm/mm/proc-v6.S
15 #include <asm/asm-offsets.h>
17 #include <asm/pgtable-hwdef.h>
19 #include "proc-macros.S"
46 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
53  *	Perform a soft reset of the system.  Put the CPU into the
54  *	same state as it would be if it had been reset, and branch
55  *	to what would be the reset vector.
57  *	- loc   - location to jump to for soft reset
64 	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
80 	mcr	p15, 0, r1, c7, c10, 4		@ DWB - WFI may enter a low-power mode
98  *	- pgd_phys - physical address of new TTB
101  *	- we are not using split page tables
106 	mmid	r1, r1				@ get mm->context.id
128  *	- ptep  - pointer to level 2 translation table entry
129  *		  (hardware version is stored at -1024 bytes)
130  *	- pte   - PTE value to store
131  *	- ext	- value for extended PTE bits
142 /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
147 	stmfd	sp!, {r4 - r9, lr}
154 	mrc	p15, 0, r8, c1, c0, 2	@ co-processor access control
156 	stmia	r0, {r4 - r9}
157 	ldmfd	sp!, {r4- r9, pc}
167 	ldmia	r0, {r4 - r9}
178 	mcr	p15, 0, r8, c1, c0, 2	@ co-processor access control
185 	string	cpu_v6_name, "ARMv6-compatible processor"
192  *	Initialise TLB, Caches, and MMU state ready to switch the MMU
202  *	- cache type register is implemented
230  ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
237 	 * corruption with hit-under-miss enabled). The conditional code below
239 	 * and the FI bit in the control register) disables hit-under-miss
264 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
306 	.size	__v6_proc_info, . - __v6_proc_info