Lines Matching full:p15
48 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
74 mcr p15, 1, r0, c15, c9, 0 @ clean L2
75 mcr p15, 0, r0, c7, c10, 4 @ drain WB
78 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 mcr p15, 0, r0, c1, c0, 0 @ disable caches
98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
99 mcr p15, 0, ip, c7, c10, 4 @ drain WB
101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
119 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
131 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
156 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
164 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
165 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
185 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
186 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
188 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
189 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
195 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
228 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
229 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
233 mcr p15, 0, r0, c7, c10, 4 @ drain WB
250 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
255 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
256 mcr p15, 0, r0, c7, c10, 4 @ drain WB
266 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
267 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
270 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
271 mcr p15, 0, r0, c7, c10, 4 @ drain WB
292 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
294 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
295 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
299 mcr p15, 0, r0, c7, c10, 4 @ drain WB
306 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
308 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
313 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
314 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
331 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
335 mcr p15, 0, r0, c7, c10, 4 @ drain WB
345 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
346 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
348 mcr p15, 0, r0, c7, c10, 4 @ drain WB
362 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
366 mcr p15, 0, r0, c7, c10, 4 @ drain WB
377 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
378 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
380 mcr p15, 0, r0, c7, c10, 4 @ drain WB
429 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
435 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
440 mcr p15, 0, r0, c7, c10, 4 @ drain WB
466 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
467 mcreq p15, 0, ip, c7, c10, 4 @ drain WB
469 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
470 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
487 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
490 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
492 mcr p15, 0, r0, c7, c10, 4 @ drain WB
503 mrc p15, 0, r4, c13, c0, 0 @ PID
504 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
505 mrc p15, 0, r6, c1, c0, 0 @ Control register
512 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
513 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
515 mcr p15, 0, r4, c13, c0, 0 @ PID
516 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
517 mcr p15, 0, r1, c2, c0, 0 @ TTB address
526 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
527 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
529 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
534 mrc p15, 0, r0, c1, c0 @ get control register v4