Lines Matching full:p15

48 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
51 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
63 	mcr	p15, 0, ip, c7, c5, 0		@ flush I cache
64 	mcr	p15, 0, ip, c7, c6, 0		@ flush D cache
65 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
66 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
69 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
79 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
90 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
109 	mcr	p15, 0, ip, c7, c6, 0		@ flush D cache
113 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean/flush D index
120 	mcrne	p15, 0, ip, c7, c5, 0		@ flush I cache
121 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
144 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
145 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
147 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
148 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
151 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
152 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
154 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
155 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
161 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
194 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
195 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
199 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
216 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
221 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
222 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
241 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
243 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
246 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
250 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
266 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
271 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
288 	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
290 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
295 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
325 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
330 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
337 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
338 	mcr	p15, 0, r0, c7, c6, 0		@ invalidate D cache
339 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
341 	mcr	p15, 0, r0, c6, c3, 0		@ disable memory region 3~7
342 	mcr	p15, 0, r0, c6, c4, 0
343 	mcr	p15, 0, r0, c6, c5, 0
344 	mcr	p15, 0, r0, c6, c6, 0
345 	mcr	p15, 0, r0, c6, c7, 0
348 	mcr	p15, 0, r0, c6,	c0, 0		@ set region 0, default
353 	mcr	p15, 0, r3, c6, c1, 0
358 	mcr	p15, 0, r3, c6, c2, 0
361 	mcr	p15, 0, r0, c2, c0, 0		@ region 1,2 d-cacheable
362 	mcr	p15, 0, r0, c2, c0, 1		@ region 1,2 i-cacheable
368 	mcr	p15, 0, r0, c3, c0, 0
381 	mcr	p15, 0, r0, c5, c0, 2		@ set data access permission
382 	mcr	p15, 0, r0, c5, c0, 3		@ set inst. access permission
384 	mrc	p15, 0, r0, c1, c0		@ get control register