Lines Matching full:r0
83 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
84 bic r0, r0, #0x1000 @ ...i............
85 bic r0, r0, #0x000e @ ............wca.
86 mcr p15, 0, r0, c1, c0, 0 @ disable caches
121 ret r0
130 mov r0, #0
132 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
135 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
146 mov r0, #0
147 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
195 sub r3, r1, r0 @ calculate total size
200 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
201 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
202 add r0, r0, #CACHE_DLINESIZE
203 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
205 add r0, r0, #CACHE_DLINESIZE
207 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
208 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 add r0, r0, #CACHE_DLINESIZE
210 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
212 add r0, r0, #CACHE_DLINESIZE
214 cmp r0, r1
248 bic r0, r0, #CACHE_DLINESIZE - 1
249 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
250 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
251 add r0, r0, #CACHE_DLINESIZE
252 cmp r0, r1
254 mcr p15, 0, r0, c7, c10, 4 @ drain WB
255 mov r0, #0
269 add r1, r0, r1
270 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
271 add r0, r0, #CACHE_DLINESIZE
272 cmp r0, r1
274 mov r0, #0
275 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
276 mcr p15, 0, r0, c7, c10, 4 @ drain WB
295 tst r0, #CACHE_DLINESIZE - 1
296 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
300 bic r0, r0, #CACHE_DLINESIZE - 1
301 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
302 add r0, r0, #CACHE_DLINESIZE
303 cmp r0, r1
305 mcr p15, 0, r0, c7, c10, 4 @ drain WB
320 bic r0, r0, #CACHE_DLINESIZE - 1
321 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
322 add r0, r0, #CACHE_DLINESIZE
323 cmp r0, r1
326 mcr p15, 0, r0, c7, c10, 4 @ drain WB
338 bic r0, r0, #CACHE_DLINESIZE - 1
341 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
343 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
345 add r0, r0, #CACHE_DLINESIZE
346 cmp r0, r1
348 mcr p15, 0, r0, c7, c10, 4 @ drain WB
359 add r1, r1, r0
378 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
379 add r0, r0, #CACHE_DLINESIZE
383 mcr p15, 0, r0, c7, c10, 4 @ drain WB
411 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
426 mov r0, r0
428 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
430 mcr p15, 0, r0, c7, c10, 4 @ drain WB
437 mov r0, #0
440 orr r0,r0,#1 << 1 @ transparent mode on
441 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
443 mov r0, #0
444 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
445 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
447 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
451 mov r0, #4 @ disable write-back on caches explicitly
452 mcr p15, 7, r0, c15, c0, 0
457 mrc p15, 0, r0, c1, c0 @ get control register v4
458 bic r0, r0, r5
459 orr r0, r0, r6
461 orr r0, r0, #0x4000 @ .1.. .... .... ....