Lines Matching +full:cache +full:- +full:unified
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v6.S
16 #include "proc-macros.S"
28 * Flush the whole I-cache.
30 * ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
35 * r0 - set to 0
36 * r1 - corrupted
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
60 * Flush the entire cache.
67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
84 * - mm - mm_struct describing address space
95 * - start - start address (may not be aligned)
96 * - end - end address (exclusive, may not be aligned)
97 * - flags - vm_area_struct flags describing address space
100 * - we have a VIPT cache.
113 * - start - virtual start address of region
114 * - end - virtual end address of region
117 * - the Icache does not read data from the write buffer
132 * - start - virtual start address of region
133 * - end - virtual end address of region
136 * - the Icache does not read data from the write buffer
141 bic r0, r0, #CACHE_LINE_SIZE - 1
152 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
162 * Fault handling for the cache operation above. If the virtual address in r0
163 * isn't mapped, fail with -EFAULT.
166 mov r0, #-EFAULT
177 * - addr - kernel address
178 * - size - region size
182 bic r0, r0, #D_CACHE_LINE_SIZE - 1
187 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
202 * Invalidate the data cache within the specified region; we will
204 * purge old data in the cache.
206 * - start - virtual start address of region
207 * - end - virtual end address of region
210 tst r0, #D_CACHE_LINE_SIZE - 1
211 bic r0, r0, #D_CACHE_LINE_SIZE - 1
215 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
217 tst r1, #D_CACHE_LINE_SIZE - 1
218 bic r1, r1, #D_CACHE_LINE_SIZE - 1
222 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
228 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
239 * - start - virtual start address of region
240 * - end - virtual end address of region
243 bic r0, r0, #D_CACHE_LINE_SIZE - 1
248 mcr p15, 0, r0, c7, c11, 1 @ clean unified line
259 * - start - virtual start address of region
260 * - end - virtual end address of region
263 bic r0, r0, #D_CACHE_LINE_SIZE - 1
280 * - start - kernel virtual start address
281 * - size - size of region
282 * - dir - DMA direction
293 * - start - kernel virtual start address
294 * - size - size of region
295 * - dir - DMA direction