Lines Matching +full:disable +full:- +full:mmu +full:- +full:reset
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
15 #include <asm/proc-fns.h>
20 #include "reset.h"
50 .arch armv7-a
89 * puts the current cpu in reset
102 * r0 is cpu to reset
104 * puts the specified CPU in wait-for-event mode on the flow controller
105 * and puts the CPU in reset
110 * corrupts r0-r3, r12
126 str r1, [r3, #0x340] @ put slave CPU in reset
140 * Enters suspend in LP0 or LP1 by turning off the mmu and jumping to
145 /* Flush, disable the L1 data cache and exit SMP */
165 * Switches the CPU cluster to PLL-P and enters sleep.
180 * reset vector for LP1 restore; copied into IRAM during suspend.
182 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLP,
239 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP
267 * puts memory in self-refresh for LP0 and LP1
282 * start by switching to CLKM to safely disable PLLs, then switch to
302 /* disable PLLM, PLLP and PLLC */
346 * called with MMU off and caches disabled
370 bne emcself @ loop until DDR in self-refresh
409 .word tegra20_sdram_pad_size - tegra20_sdram_pad_address
424 .rept (tegra20_sdram_pad_size - tegra20_sdram_pad_address) / 4