Lines Matching full:ceil
349 #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
352 #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
355 /* fua = fxtl/(16*Ceil (Div/16)) */
356 /* Tua = 16*Ceil (Div/16)*Txtl */
488 #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
491 #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
494 /* fsd = fxtl/(16*Ceil (Div/16)) */
495 /* Tsd = 16*Ceil (Div/16)*Txtl */
646 #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \
648 /* faud = fmc/(32*Ceil (Div/32)) */
649 /* Taud = 32*Ceil (Div/32)*Tmc */
659 #define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \
661 /* ftcm = fmc/(32*Ceil (Div/32)) */
662 /* Ttcm = 32*Ceil (Div/32)*Tmc */
778 #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \
780 /* fss = fxtl/(2*Ceil (Div/2)) */
781 /* Tss = 2*Ceil (Div/2)*Txtl */
1388 #define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \
1393 #define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \
1471 #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
1476 #define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \
1483 #define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \
1488 #define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \
1494 #define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \
1523 #define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \
1529 #define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \
1534 #define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \
1758 #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
1760 /* fpix = fcpu/(2*Ceil (Div/2)) */
1761 /* Tpix = 2*Ceil (Div/2)*Tcpu */
1768 #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
1770 /* fac = fln/(2*Ceil (Div/2)) */
1771 /* Tac = 2*Ceil (Div/2)*Tln */