Lines Matching +full:refresh +full:- +full:rate +full:- +full:hz

1 /* SPDX-License-Identifier: GPL-2.0-only */
8  * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
9  * Copyright (C) 2007-2008 Nokia Corporation
55  * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
56  * @rate: SDRC clock rate (in Hz)
57  * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
58  * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
59  * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
60  * @mr: Value to program to SDRC_MR for this rate
62  * This structure holds a pre-computed set of register values for the
63  * SDRC for a given SDRC clock rate and SDRAM chip.  These are
64  * intended to be pre-computed and specified in an array in the board-*.c
65  * files.  The structure is keyed off the 'rate' field.
68 	unsigned long rate;  member
112 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
124 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
158  * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
166  * become sub-optimal. The RFR value goes in the opposite direction. If you
167  * don't adjust it down as your clock period increases the refresh interval
173  * Only the FULL speed values are given. Current code is such that rate
198 /* SMS register offsets - read/write with sms_{read,write}_reg() */