28 #define TZIC_INTCNTL	0x0000	/* Control register */
29 #define TZIC_INTTYPE	0x0004	/* Controller Type register */
30 #define TZIC_IMPID	0x0008	/* Distributor Implementer Identification */
31 #define TZIC_PRIOMASK	0x000C	/* Priority Mask Reg */
32 #define TZIC_SYNCCTRL	0x0010	/* Synchronizer Control register */
33 #define TZIC_DSMINT	0x0014	/* DSM interrupt Holdoffregister */
34 #define TZIC_INTSEC0(i)	(0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
35 #define TZIC_ENSET0(i)	(0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
36 #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
37 #define TZIC_SRCSET0	0x0200	/* Source Set Register 0 */
38 #define TZIC_SRCCLAR0	0x0280	/* Source Clear Register 0 */
39 #define TZIC_PRIORITY0	0x0400	/* Priority Register 0 */
40 #define TZIC_PND0	0x0D00	/* Pending Register 0 */
41 #define TZIC_HIPND(i)	(0x0D80+ ((i) << 2))	/* High Priority Pending Register */
42 #define TZIC_WAKEUP0(i)	(0x0E00 + ((i) << 2))	/* Wakeup Config Register */
43 #define TZIC_SWINT	0x0F00	/* Software Interrupt Rigger Register */
44 #define TZIC_ID0	0x0FD0	/* Indentification Register 0 */
59 	mask = 1U << (hwirq & 0x1F);  in tzic_set_irq_fiq()
66 	return 0;  in tzic_set_irq_fiq()
119 	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);  in tzic_init_gc()
128 		handled = 0;  in tzic_handle_irq()
130 		for (i = 0; i < 4; i++) {  in tzic_handle_irq()
154 	tzic_base = of_iomap(np, 0);  in tzic_init_dt()
162 	imx_writel(0x80010001, tzic_base + TZIC_INTCNTL);  in tzic_init_dt()
163 	imx_writel(0x1f, tzic_base + TZIC_PRIOMASK);  in tzic_init_dt()
164 	imx_writel(0x02, tzic_base + TZIC_SYNCCTRL);  in tzic_init_dt()
166 	for (i = 0; i < 4; i++)  in tzic_init_dt()
167 		imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));  in tzic_init_dt()
170 	for (i = 0; i < 4; i++)  in tzic_init_dt()
171 		imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));  in tzic_init_dt()
175 	irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());  in tzic_init_dt()
176 	WARN_ON(irq_base < 0);  in tzic_init_dt()
178 	domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,  in tzic_init_dt()
182 	for (i = 0; i < 4; i++, irq_base += 32)  in tzic_init_dt()
194 	return 0;  in tzic_init_dt()
201  * @return			0 if successful; non-zero otherwise
212 	if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0))  in tzic_enable_wake()
215 	for (i = 0; i < 4; i++)  in tzic_enable_wake()
219 	return 0;  in tzic_enable_wake()