Lines Matching +full:non +full:- +full:pc
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/entry-armv.S
6 * ARM700 fix by Matthew Godbolt (linux-[email protected])
9 * Low-level vector interface routines
19 #include <asm/glue-df.h>
20 #include <asm/glue-pf.h>
27 #include <asm/uaccess-asm.h>
30 #include "entry-header.S"
81 @ Call the processor-specific abort handler:
83 @ r2 - pt_regs
84 @ r4 - aborted context pc
85 @ r5 - aborted context psr
105 ARM( stmib sp, {r1 - lr} )
106 THUMB( stmia sp, {r0 - r12} )
135 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
140 ldmia r0, {r4 - r6}
142 mov r7, #-1 @ "" "" "" ""
144 stmia r0, {r5 - r7} @ lr_<exception>,
168 UNWIND(.save {r0 - pc} )
181 ARM( stmib sp, {r1 - r12} )
182 THUMB( stmia sp, {r0 - r12} ) @ No STMIB in Thumb-2
184 ldmia r0, {r3 - r5}
186 mov r6, #-1 @ "" "" "" ""
197 @ r2 - sp_svc
198 @ r3 - lr_svc
199 @ r4 - lr_<exception>, already fixed up for correct return/restart
200 @ r5 - spsr_<exception>
201 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
203 stmia r7, {r2 - r6}
256 @ Correct the PC such that it is pointing at the instruction
258 @ the PC will be pointing at the next instruction, and have to
259 @ subtract 4. Otherwise, it is Thumb, and the PC will be
279 mov r1, #4 @ PC correction to apply
281 THUMB( movne r1, #2 ) @ if so, fix up PC correction
331 stmfd sp!, {r1 - r2}
336 ldmfd sp!, {r1 - r2}
353 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE
364 ARM( stmib sp, {r1 - r12} )
365 THUMB( stmia sp, {r0 - r12} )
370 ldmia r0, {r3 - r5}
372 mov r6, #-1 @ "" "" "" ""
380 @ r4 - lr_<exception>, already fixed up for correct return/restart
381 @ r5 - spsr_<exception>
382 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
386 stmia r0, {r4 - r6}
388 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
416 #warning "NPTL on non MMU needs fixing"
516 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
517 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
554 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
557 ldmia r4, {r4 - sl, fp, ip, lr} @ Load all regs saved previously
597 @ involving the PC, and decorate them with PC-relative group
603 THUMB( bx pc )
608 str sp, [ip, #-4]! @ Preserve original SP value
614 push {fp, ip, lr, pc} @ GCC flavor frame record
616 str ip, [sp, #-8]! @ store original SP
626 UNWIND( .save {sp, pc} )
655 * Each segment is 32-byte aligned and will be moved to the top of the high
673 .if (. - \sym) & 3
674 .rept 4 - (. - \sym) & 3
678 .rept (\size - (. - \sym)) / 4
730 ldmfd sp!, {r4, r5, r6, pc}
740 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
742 rsbscs r8, r8, #(2b - 1b)
751 #warning "NPTL on non MMU needs fixing"
752 mov r0, #-1
780 * the IRQ and data abort exception handlers to set the pc back
798 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
800 rsbscs r8, r8, #(2b - 1b)
806 #warning "NPTL on non MMU needs fixing"
807 mov r0, #-1
821 /* beware -- each __kuser slot must be 8 instructions max */
830 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
839 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
856 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
858 * SP points to a minimal amount of processor-private memory, the address
866 @ isb not needed due to "movs pc, lr" in the vector stub
875 @ Save r0, lr_<exception> (parent PC)
897 ARM( ldr lr, [pc, lr, lsl #2] )
898 movs pc, lr @ branch to handler in SVC mode
909 @ Save r0, lr_<exception> (parent PC)
918 @ isb not needed due to "movs pc, lr" in the vector stub
973 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
996 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1019 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1044 *-----------------------------------------------------------------------------
1046 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1054 *-----------------------------------------------------------------------------
1087 W(ldr) pc, .
1101 W(ldr) pc, .
1114 W(ldr) pc, .