Lines Matching +full:bl +full:- +full:code +full:- +full:offset
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/entry-armv.S
6 * ARM700 fix by Matthew Godbolt (linux-[email protected])
9 * Low-level vector interface routines
19 #include <asm/glue-df.h>
20 #include <asm/glue-pf.h>
27 #include <asm/uaccess-asm.h>
30 #include "entry-header.S"
58 bl generic_handle_arch_irq
64 bl call_with_stack
71 ldr_va ip, processor, offset=PROCESSOR_PABT_FUNC
74 bl CPU_PABORT_HANDLER
81 @ Call the processor-specific abort handler:
83 @ r2 - pt_regs
84 @ r4 - aborted context pc
85 @ r5 - aborted context psr
91 ldr_va ip, processor, offset=PROCESSOR_DABT_FUNC
94 bl CPU_DABORT_HANDLER
105 ARM( stmib sp, {r1 - lr} )
106 THUMB( stmia sp, {r0 - r12} )
135 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
140 ldmia r0, {r4 - r6}
142 mov r7, #-1 @ "" "" "" ""
144 stmia r0, {r5 - r7} @ lr_<exception>,
156 #define SPFIX(code...) code argument
158 #define SPFIX(code...) argument
168 UNWIND(.save {r0 - pc} )
181 ARM( stmib sp, {r1 - r12} )
182 THUMB( stmia sp, {r0 - r12} ) @ No STMIB in Thumb-2
184 ldmia r0, {r3 - r5}
186 mov r6, #-1 @ "" "" "" ""
197 @ r2 - sp_svc
198 @ r3 - lr_svc
199 @ r4 - lr_<exception>, already fixed up for correct return/restart
200 @ r5 - spsr_<exception>
201 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
203 stmia r7, {r2 - r6}
210 bl trace_hardirqs_off
248 1: bl preempt_schedule_irq @ irq en/disable is done inside
283 bl __und_fault
305 bl handle_fiq_as_nmi
331 stmfd sp!, {r1 - r2}
334 bl handle_fiq_as_nmi
336 ldmfd sp!, {r1 - r2}
353 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE
364 ARM( stmib sp, {r1 - r12} )
365 THUMB( stmia sp, {r0 - r12} )
370 ldmia r0, {r3 - r5}
372 mov r6, #-1 @ "" "" "" ""
380 @ r4 - lr_<exception>, already fixed up for correct return/restart
381 @ r5 - spsr_<exception>
382 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
386 stmia r0, {r4 - r6}
388 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
407 bl trace_hardirqs_off
466 bl call_fpe @ returns via R9 on success
471 bl __und_fault
484 * This is the return code to user mode for abort handlers
501 bl handle_fiq_as_nmi
503 restore_user_regs fast = 0, offset = 0
516 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
517 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
546 bl atomic_notifier_call_chain
554 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
557 ldmia r4, {r4 - sl, fp, ip, lr} @ Load all regs saved previously
597 @ involving the PC, and decorate them with PC-relative group
608 str sp, [ip, #-4]! @ Preserve original SP value
616 str ip, [sp, #-8]! @ store original SP
644 bl handle_bad_stack
655 * Each segment is 32-byte aligned and will be moved to the top of the high
673 .if (. - \sym) & 3
674 .rept 4 - (. - \sym) & 3
678 .rept (\size - (. - \sym)) / 4
740 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
742 rsbscs r8, r8, #(2b - 1b)
752 mov r0, #-1
779 * of the critical sequence. To prevent this, code is added to
798 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
800 rsbscs r8, r8, #(2b - 1b)
807 mov r0, #-1
821 /* beware -- each __kuser slot must be 8 instructions max */
830 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
832 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
839 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
851 * This code is copied to 0xffff1000 so we can use branches in the
852 * vectors, rather than ldr's. Note that this code must not exceed
858 * SP points to a minimal amount of processor-private memory, the address
891 @ the branch table must immediately follow this code
1044 *-----------------------------------------------------------------------------
1046 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1054 *-----------------------------------------------------------------------------