Lines Matching +full:gpio +full:- +full:mouse
1 /* SPDX-License-Identifier: GPL-2.0 */
7 * This file contains definitions for the SA-1111 Companion Chip.
8 * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
10 * Macro that calculates real address for registers in the SA-1111
50 * - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
51 * - The Feb 2001 errata (278260-010) says that the previous errata
52 * (278260-009) is wrong, and its bit actually 12, fixed in spec
53 * 278242-003.
54 * - The SA1111 manual (278242) says bit 12, but 0 to enable.
55 * - Reality is bit 13, 1 to enable.
56 * -- rmk
80 * SKPMC PS/2 Mouse Clock Divider Register
116 * SACR2 Serial Audio AC-link Control Register
118 * SASR1 Serial Audio AC-link Interface & FIFO Status Register
122 * ACCAR AC-link Command Address Register
123 * ACCDR AC-link Command Data Register
124 * ACSAR AC-link Status Address Register
125 * ACSDR AC-link Status Data Register
137 * SADR Serial Audio Data Register (16 x 32-bit)
261 * General-Purpose I/O Interface
264 * PA_DDR GPIO Block A Data Direction
265 * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write)
266 * PA_SDR GPIO Block A Sleep Direction
267 * PA_SSR GPIO Block A Sleep State
268 * PB_DDR GPIO Block B Data Direction
269 * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write)
270 * PB_SDR GPIO Block B Sleep Direction
271 * PB_SSR GPIO Block B Sleep State
272 * PC_DDR GPIO Block C Data Direction
273 * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write)
274 * PC_SDR GPIO Block C Sleep Direction
275 * PC_SSR GPIO Block C Sleep State
334 * WAKE_EN0 Wake-up source enable 0
335 * WAKE_EN1 Wake-up source enable 1
336 * WAKE_POL0 Wake-up polarity selection 0
337 * WAKE_POL1 Wake-up polarity selection 1
360 /* PS/2 Trackpad and Mouse Interfaces */
397 #define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev)
398 #define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
409 #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
435 int irq_base; /* base for cascaded on-chip IRQs */