Lines Matching +full:0 +full:xc40
10 reg = <0xa00>;
13 #size-cells = <0>;
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
16 reg = <0>;
17 #clock-cells = <0>;
26 reg = <0xa40>;
29 #size-cells = <0>;
33 #clock-cells = <0>;
37 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
42 #clock-cells = <0>;
48 #clock-cells = <0>;
57 reg = <0xa10>;
60 #size-cells = <0>;
64 #clock-cells = <0>;
70 ssi_ick: clock-ssi-ick-3430es2@0 {
71 reg = <0>;
72 #clock-cells = <0>;
80 #clock-cells = <0>;
89 reg = <0xc00>;
92 #size-cells = <0>;
96 #clock-cells = <0>;
104 #clock-cells = <0>;
112 #clock-cells = <0>;
120 #clock-cells = <0>;
128 #clock-cells = <0>;
136 #clock-cells = <0>;
144 #clock-cells = <0>;
152 #clock-cells = <0>;
160 #clock-cells = <0>;
168 #clock-cells = <0>;
177 reg = <0xc40>;
180 #size-cells = <0>;
184 #clock-cells = <0>;
193 #clock-cells = <0>;
200 reg = <0xc10>;
203 #size-cells = <0>;
207 #clock-cells = <0>;