Lines Matching +full:0 +full:d00
8 dpll4_ck: dpll4_ck@d00 {
9 #clock-cells = <0>;
12 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
15 dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
16 #clock-cells = <0>;
19 ti,bit-shift = <0x1e>;
20 reg = <0x0d00>;
25 dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
26 #clock-cells = <0>;
29 ti,bit-shift = <0x1b>;
30 reg = <0x0d00>;
34 dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
35 #clock-cells = <0>;
38 ti,bit-shift = <0xc>;
39 reg = <0x0d00>;
43 dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
44 #clock-cells = <0>;
47 ti,bit-shift = <0x1c>;
48 reg = <0x0d00>;
52 dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
53 #clock-cells = <0>;
56 ti,bit-shift = <0x1f>;
57 reg = <0x0d00>;
63 reg = <0x1000>;
66 #size-cells = <0>;
70 #clock-cells = <0>;