Lines Matching +full:sysc +full:- +full:omap2
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
20 interrupt-parent = <&crossbar_mpu>;
47 compatible = "arm,armv7-timer";
53 interrupt-parent = <&gic>;
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
58 interrupt-controller;
59 #interrupt-cells = <3>;
65 interrupt-parent = <&gic>;
68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 interrupt-controller;
71 #interrupt-cells = <3>;
73 interrupt-parent = <&gic>;
77 #address-cells = <1>;
78 #size-cells = <0>;
82 compatible = "arm,cortex-a15";
85 operating-points-v2 = <&cpu0_opp_table>;
88 clock-names = "cpu";
90 clock-latency = <300000>; /* From omap-cpufreq driver */
93 #cooling-cells = <2>; /* min followed by max */
95 vbb-supply = <&abb_mpu>;
99 cpu0_opp_table: opp-table {
100 compatible = "operating-points-v2-ti-cpu";
103 opp-1000000000 {
105 opp-hz = /bits/ 64 <1000000000>;
106 opp-microvolt = <1060000 850000 1150000>,
108 opp-supported-hw = <0xFF 0x01>;
109 opp-suspend;
112 opp-1176000000 {
114 opp-hz = /bits/ 64 <1176000000>;
115 opp-microvolt = <1160000 885000 1160000>,
118 opp-supported-hw = <0xFF 0x02>;
121 opp-1500000000 {
123 opp-hz = /bits/ 64 <1500000000>;
124 opp-microvolt = <1210000 950000 1250000>,
126 opp-supported-hw = <0xFF 0x04>;
138 compatible = "simple-pm-bus";
139 power-domains = <&prm_core>;
142 #address-cells = <1>;
143 #size-cells = <1>;
145 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
147 l3-noc@44000000 {
148 compatible = "ti,dra7-l3-noc";
151 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
162 target-module@48210000 {
163 compatible = "ti,sysc-omap4-simple", "ti,sysc";
164 power-domains = <&prm_mpu>;
166 clock-names = "fck";
167 #address-cells = <1>;
168 #size-cells = <1>;
172 compatible = "ti,omap5-mpu";
184 * 26-678. Main Sequence PCIe Controller Global Initialization"
187 axi0: target-module@51000000 {
188 compatible = "ti,sysc-omap4", "ti,sysc";
189 power-domains = <&prm_l3init>;
191 reset-names = "rstctrl";
195 clock-names = "fck", "phy-clk", "phy-clk-div";
196 #size-cells = <1>;
197 #address-cells = <1>;
200 dma-ranges;
209 reg-names = "rc_dbics", "ti_conf", "config";
211 #address-cells = <3>;
212 #size-cells = <2>;
216 bus-range = <0x00 0xff>;
217 #interrupt-cells = <1>;
218 num-lanes = <1>;
219 linux,pci-domain = <0>;
221 phy-names = "pcie-phy0";
222 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
223 interrupt-map-mask = <0 0 0 7>;
224 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
228 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
230 pcie1_intc: interrupt-controller {
231 interrupt-controller;
232 #address-cells = <0>;
233 #interrupt-cells = <1>;
242 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
244 num-lanes = <1>;
245 num-ib-windows = <4>;
246 num-ob-windows = <16>;
248 phy-names = "pcie-phy0";
249 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
250 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
258 * 26-678. Main Sequence PCIe Controller Global Initialization"
261 axi1: target-module@51800000 {
262 compatible = "ti,sysc-omap4", "ti,sysc";
266 clock-names = "fck", "phy-clk", "phy-clk-div";
267 power-domains = <&prm_l3init>;
269 reset-names = "rstctrl";
270 #size-cells = <1>;
271 #address-cells = <1>;
274 dma-ranges;
280 reg-names = "rc_dbics", "ti_conf", "config";
282 #address-cells = <3>;
283 #size-cells = <2>;
287 bus-range = <0x00 0xff>;
288 #interrupt-cells = <1>;
289 num-lanes = <1>;
290 linux,pci-domain = <1>;
292 phy-names = "pcie-phy0";
293 interrupt-map-mask = <0 0 0 7>;
294 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
298 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
299 pcie2_intc: interrupt-controller {
300 interrupt-controller;
301 #address-cells = <0>;
302 #interrupt-cells = <1>;
308 compatible = "mmio-sram";
311 #address-cells = <1>;
312 #size-cells = <1>;
324 sram-hs@0 {
325 compatible = "ti,secure-ram";
338 compatible = "mmio-sram";
341 #address-cells = <1>;
342 #size-cells = <1>;
347 compatible = "mmio-sram";
350 #address-cells = <1>;
351 #size-cells = <1>;
361 compatible = "ti,dra752-bandgap";
363 #thermal-sensor-cells = <1>;
372 compatible = "ti,dra7-iodelay";
374 #address-cells = <1>;
375 #size-cells = <0>;
376 #pinctrl-cells = <2>;
379 target-module@43300000 {
380 compatible = "ti,sysc-omap4", "ti,sysc";
383 reg-names = "rev", "sysc";
384 ti,sysc-midle = <SYSC_IDLE_FORCE>,
387 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
391 clock-names = "fck";
392 #address-cells = <1>;
393 #size-cells = <1>;
397 compatible = "ti,edma3-tpcc";
399 reg-names = "edma3_cc";
403 interrupt-names = "edma3_ccint", "edma3_mperr",
405 dma-requests = <64>;
406 #dma-cells = <2>;
412 * ti,edma-memcpy-channels = <20 21>;
419 target-module@43400000 {
420 compatible = "ti,sysc-omap4", "ti,sysc";
423 reg-names = "rev", "sysc";
424 ti,sysc-midle = <SYSC_IDLE_FORCE>,
427 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
431 clock-names = "fck";
432 #address-cells = <1>;
433 #size-cells = <1>;
437 compatible = "ti,edma3-tptc";
440 interrupt-names = "edma3_tcerrint";
444 target-module@43500000 {
445 compatible = "ti,sysc-omap4", "ti,sysc";
448 reg-names = "rev", "sysc";
449 ti,sysc-midle = <SYSC_IDLE_FORCE>,
452 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
456 clock-names = "fck";
457 #address-cells = <1>;
458 #size-cells = <1>;
462 compatible = "ti,edma3-tptc";
465 interrupt-names = "edma3_tcerrint";
469 target-module@4e000000 {
470 compatible = "ti,sysc-omap2", "ti,sysc";
473 reg-names = "rev", "sysc";
474 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
478 #size-cells = <1>;
479 #address-cells = <1>;
482 compatible = "ti,omap5-dmm";
489 compatible = "ti,dra7-ipu";
491 reg-names = "l2ram";
496 firmware-name = "dra7-ipu1-fw.xem4";
500 compatible = "ti,dra7-ipu";
502 reg-names = "l2ram";
507 firmware-name = "dra7-ipu2-fw.xem4";
511 compatible = "ti,dra7-dsp";
515 reg-names = "l2ram", "l1pram", "l1dram";
521 firmware-name = "dra7-dsp1-fw.xe66";
524 target-module@40d01000 {
525 compatible = "ti,sysc-omap2", "ti,sysc";
529 reg-names = "rev", "sysc", "syss";
530 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
533 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
537 clock-names = "fck";
539 reset-names = "rstctrl";
541 #size-cells = <1>;
542 #address-cells = <1>;
545 compatible = "ti,dra7-dsp-iommu";
548 #iommu-cells = <0>;
549 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
553 target-module@40d02000 {
554 compatible = "ti,sysc-omap2", "ti,sysc";
558 reg-names = "rev", "sysc", "syss";
559 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
562 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
566 clock-names = "fck";
568 reset-names = "rstctrl";
570 #size-cells = <1>;
571 #address-cells = <1>;
574 compatible = "ti,dra7-dsp-iommu";
577 #iommu-cells = <0>;
578 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
582 target-module@58882000 {
583 compatible = "ti,sysc-omap2", "ti,sysc";
587 reg-names = "rev", "sysc", "syss";
588 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
591 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
595 clock-names = "fck";
597 reset-names = "rstctrl";
598 #address-cells = <1>;
599 #size-cells = <1>;
603 compatible = "ti,dra7-iommu";
606 #iommu-cells = <0>;
607 ti,iommu-bus-err-back;
611 target-module@55082000 {
612 compatible = "ti,sysc-omap2", "ti,sysc";
616 reg-names = "rev", "sysc", "syss";
617 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
620 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
624 clock-names = "fck";
626 reset-names = "rstctrl";
627 #address-cells = <1>;
628 #size-cells = <1>;
632 compatible = "ti,dra7-iommu";
635 #iommu-cells = <0>;
636 ti,iommu-bus-err-back;
640 abb_mpu: regulator-abb-mpu@4ae07ddc {
641 compatible = "ti,abb-v3";
642 regulator-name = "abb_mpu";
643 #address-cells = <0>;
644 #size-cells = <0>;
646 ti,settling-time = <50>;
647 ti,clock-cycles = <16>;
652 reg-names = "setup-address", "control-address",
653 "int-address", "efuse-address",
654 "ldo-address";
655 ti,tranxdone-status-mask = <0x80>;
657 ti,ldovbb-override-mask = <0x400>;
659 ti,ldovbb-vset-mask = <0x1F>;
673 abb_ivahd: regulator-abb-ivahd@4ae07e34 {
674 compatible = "ti,abb-v3";
675 regulator-name = "abb_ivahd";
676 #address-cells = <0>;
677 #size-cells = <0>;
679 ti,settling-time = <50>;
680 ti,clock-cycles = <16>;
685 reg-names = "setup-address", "control-address",
686 "int-address", "efuse-address",
687 "ldo-address";
688 ti,tranxdone-status-mask = <0x40000000>;
690 ti,ldovbb-override-mask = <0x400>;
692 ti,ldovbb-vset-mask = <0x1F>;
706 abb_dspeve: regulator-abb-dspeve@4ae07e30 {
707 compatible = "ti,abb-v3";
708 regulator-name = "abb_dspeve";
709 #address-cells = <0>;
710 #size-cells = <0>;
712 ti,settling-time = <50>;
713 ti,clock-cycles = <16>;
718 reg-names = "setup-address", "control-address",
719 "int-address", "efuse-address",
720 "ldo-address";
721 ti,tranxdone-status-mask = <0x20000000>;
723 ti,ldovbb-override-mask = <0x400>;
725 ti,ldovbb-vset-mask = <0x1F>;
739 abb_gpu: regulator-abb-gpu@4ae07de4 {
740 compatible = "ti,abb-v3";
741 regulator-name = "abb_gpu";
742 #address-cells = <0>;
743 #size-cells = <0>;
745 ti,settling-time = <50>;
746 ti,clock-cycles = <16>;
751 reg-names = "setup-address", "control-address",
752 "int-address", "efuse-address",
753 "ldo-address";
754 ti,tranxdone-status-mask = <0x10000000>;
756 ti,ldovbb-override-mask = <0x400>;
758 ti,ldovbb-vset-mask = <0x1F>;
772 target-module@4b300000 {
773 compatible = "ti,sysc-omap4", "ti,sysc";
776 reg-names = "rev", "sysc";
777 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
782 clock-names = "fck";
783 #address-cells = <1>;
784 #size-cells = <1>;
789 compatible = "ti,dra7xxx-qspi";
792 reg-names = "qspi_base", "qspi_mmap";
793 syscon-chipselects = <&scm_conf 0x558>;
794 #address-cells = <1>;
795 #size-cells = <0>;
797 clock-names = "fck";
798 num-cs = <4>;
807 target-module@50000000 {
808 compatible = "ti,sysc-omap2", "ti,sysc";
812 reg-names = "rev", "sysc", "syss";
813 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
816 ti,syss-mask = <1>;
818 clock-names = "fck";
819 #address-cells = <1>;
820 #size-cells = <1>;
825 compatible = "ti,am3352-gpmc";
829 dma-names = "rxtx";
830 gpmc,num-cs = <8>;
831 gpmc,num-waitpins = <2>;
832 #address-cells = <2>;
833 #size-cells = <1>;
834 interrupt-controller;
835 #interrupt-cells = <2>;
836 gpio-controller;
837 #gpio-cells = <2>;
842 target-module@56000000 {
843 compatible = "ti,sysc-omap4", "ti,sysc";
846 reg-names = "rev", "sysc";
847 ti,sysc-midle = <SYSC_IDLE_FORCE>,
850 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
855 clock-names = "fck";
856 #address-cells = <1>;
857 #size-cells = <1>;
861 compatible = "ti,am5728-gpu", "img,powervr-sgx544";
868 compatible = "ti,irq-crossbar";
870 interrupt-controller;
871 interrupt-parent = <&wakeupgen>;
872 #interrupt-cells = <3>;
873 ti,max-irqs = <160>;
874 ti,max-crossbar-sources = <MAX_SOURCES>;
875 ti,reg-size = <2>;
876 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
877 ti,irqs-skip = <10 133 139 140>;
878 ti,irqs-safe-map = <0>;
881 target-module@58000000 {
882 compatible = "ti,sysc-omap2", "ti,sysc";
885 reg-names = "rev", "syss";
886 ti,syss-mask = <1>;
891 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
892 #address-cells = <1>;
893 #size-cells = <1>;
897 compatible = "ti,dra7-dss";
902 syscon-pll-ctrl = <&scm_conf 0x538>;
903 #address-cells = <1>;
904 #size-cells = <1>;
907 target-module@1000 {
908 compatible = "ti,sysc-omap2", "ti,sysc";
912 reg-names = "rev", "sysc", "syss";
913 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
916 ti,sysc-midle = <SYSC_IDLE_FORCE>,
919 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
923 ti,syss-mask = <1>;
925 clock-names = "fck";
926 #address-cells = <1>;
927 #size-cells = <1>;
931 compatible = "ti,dra7-dispc";
935 clock-names = "fck";
937 syscon-pol = <&scm_conf 0x534>;
941 target-module@40000 {
942 compatible = "ti,sysc-omap4", "ti,sysc";
945 reg-names = "rev", "sysc";
946 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
950 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
953 clock-names = "fck", "dss_clk";
954 #address-cells = <1>;
955 #size-cells = <1>;
959 compatible = "ti,dra7-hdmi";
964 reg-names = "wp", "pll", "phy", "core";
969 clock-names = "fck", "sys_clk";
971 dma-names = "audio_tx";
977 target-module@59000000 {
978 compatible = "ti,sysc-omap4", "ti,sysc";
980 reg-names = "rev";
982 clock-names = "fck";
983 #address-cells = <1>;
984 #size-cells = <1>;
992 clock-names = "core";
996 aes1_target: target-module@4b500000 {
997 compatible = "ti,sysc-omap2", "ti,sysc";
1001 reg-names = "rev", "sysc", "syss";
1002 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1004 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1008 ti,syss-mask = <1>;
1011 clock-names = "fck";
1012 #address-cells = <1>;
1013 #size-cells = <1>;
1017 compatible = "ti,omap4-aes";
1021 dma-names = "tx", "rx";
1023 clock-names = "fck";
1027 aes2_target: target-module@4b700000 {
1028 compatible = "ti,sysc-omap2", "ti,sysc";
1032 reg-names = "rev", "sysc", "syss";
1033 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1035 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1039 ti,syss-mask = <1>;
1042 clock-names = "fck";
1043 #address-cells = <1>;
1044 #size-cells = <1>;
1048 compatible = "ti,omap4-aes";
1052 dma-names = "tx", "rx";
1054 clock-names = "fck";
1058 sham1_target: target-module@4b101000 {
1059 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1063 reg-names = "rev", "sysc", "syss";
1064 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1066 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1069 ti,syss-mask = <1>;
1072 clock-names = "fck";
1073 #address-cells = <1>;
1074 #size-cells = <1>;
1078 compatible = "ti,omap5-sham";
1082 dma-names = "rx";
1084 clock-names = "fck";
1088 sham2_target: target-module@42701000 {
1089 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1093 reg-names = "rev", "sysc", "syss";
1094 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1096 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1099 ti,syss-mask = <1>;
1102 clock-names = "fck";
1103 #address-cells = <1>;
1104 #size-cells = <1>;
1108 compatible = "ti,omap5-sham";
1112 dma-names = "rx";
1114 clock-names = "fck";
1118 iva_hd_target: target-module@5a000000 {
1119 compatible = "ti,sysc-omap4", "ti,sysc";
1122 reg-names = "rev", "sysc";
1123 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1126 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1129 power-domains = <&prm_iva>;
1131 reset-names = "rstctrl";
1133 clock-names = "fck";
1134 #address-cells = <1>;
1135 #size-cells = <1>;
1144 opp_supply_mpu: opp-supply@4a003b20 {
1145 compatible = "ti,omap5-opp-supply";
1147 ti,efuse-settings = <
1153 ti,absolute-max-voltage-uv = <1500000>;
1158 thermal_zones: thermal-zones {
1159 #include "omap4-cpu-thermal.dtsi"
1160 #include "omap5-gpu-thermal.dtsi"
1161 #include "omap5-core-thermal.dtsi"
1162 #include "dra7-dspeve-thermal.dtsi"
1163 #include "dra7-iva-thermal.dtsi"
1169 polling-delay = <500>; /* milliseconds */
1209 #include "dra7-l4.dtsi"
1210 #include "dra7xx-clocks.dtsi"
1214 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1216 #power-domain-cells = <0>;
1220 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1222 #reset-cells = <1>;
1223 #power-domain-cells = <0>;
1227 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1229 #reset-cells = <1>;
1230 #power-domain-cells = <0>;
1234 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1236 #power-domain-cells = <0>;
1240 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1242 #reset-cells = <1>;
1243 #power-domain-cells = <0>;
1247 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1249 #reset-cells = <1>;
1250 #power-domain-cells = <0>;
1254 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1256 #power-domain-cells = <0>;
1260 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1262 #power-domain-cells = <0>;
1266 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1268 #power-domain-cells = <0>;
1272 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1274 #reset-cells = <1>;
1275 #power-domain-cells = <0>;
1279 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1281 #power-domain-cells = <0>;
1285 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1287 #power-domain-cells = <0>;
1291 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1293 #power-domain-cells = <0>;
1297 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1299 #reset-cells = <1>;
1300 #power-domain-cells = <0>;
1304 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1306 #power-domain-cells = <0>;
1310 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1312 #power-domain-cells = <0>;
1316 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1318 #power-domain-cells = <0>;
1322 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1324 #power-domain-cells = <0>;
1328 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1330 #power-domain-cells = <0>;
1334 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1336 #power-domain-cells = <0>;
1340 /* Preferred always-on timer for clockevent */
1342 ti,no-reset-on-init;
1343 ti,no-idle;
1345 assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
1346 assigned-clock-parents = <&sys_32k_ck>;
1352 ti,no-reset-on-init;
1353 ti,no-idle;
1355 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
1356 assigned-clock-parents = <&timer_sys_clk_div>;
1361 ti,no-reset-on-init;
1362 ti,no-idle;
1364 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
1365 assigned-clock-parents = <&timer_sys_clk_div>;