Lines Matching +full:0 +full:x5a000000
60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x2000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
72 reg = <0x0 0x48281000 0x0 0x1000>;
78 #size-cells = <0>;
80 cpu0: cpu@0 {
83 reg = <0>;
108 opp-supported-hw = <0xFF 0x01>;
118 opp-supported-hw = <0xFF 0x02>;
126 opp-supported-hw = <0xFF 0x04>;
140 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>,
141 <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>;
144 ranges = <0x0 0x0 0x0 0xc0000000>;
145 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
149 reg = <0x44000000 0x1000000>,
150 <0x45000000 0x1000>;
165 clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>;
169 ranges = <0 0x48210000 0x1f0000>;
190 resets = <&prm_l3init 0>;
192 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,
198 ranges = <0x51000000 0x51000000 0x3000>,
199 <0x20000000 0x20000000 0x10000000>;
206 reg = <0x51000000 0x2000>,
207 <0x51002000 0x14c>,
208 <0x20001000 0x2000>;
210 interrupts = <0 232 0x4>, <0 233 0x4>;
214 ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>,
215 <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>;
216 bus-range = <0x00 0xff>;
219 linux,pci-domain = <0>;
222 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
223 interrupt-map-mask = <0 0 0 7>;
224 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
225 <0 0 0 2 &pcie1_intc 2>,
226 <0 0 0 3 &pcie1_intc 3>,
227 <0 0 0 4 &pcie1_intc 4>;
228 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
232 #address-cells = <0>;
238 reg = <0x51000000 0x28>,
239 <0x51002000 0x14c>,
240 <0x51001000 0x28>,
241 <0x20001000 0x10000000>;
243 interrupts = <0 232 0x4>;
249 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
250 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
263 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,
272 ranges = <0x51800000 0x51800000 0x3000>,
273 <0x30000000 0x30000000 0x10000000>;
277 reg = <0x51800000 0x2000>,
278 <0x51802000 0x14c>,
279 <0x30001000 0x2000>;
281 interrupts = <0 355 0x4>, <0 356 0x4>;
285 ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
286 <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
287 bus-range = <0x00 0xff>;
293 interrupt-map-mask = <0 0 0 7>;
294 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
295 <0 0 0 2 &pcie2_intc 2>,
296 <0 0 0 3 &pcie2_intc 3>,
297 <0 0 0 4 &pcie2_intc 4>;
298 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
301 #address-cells = <0>;
309 reg = <0x40300000 0x80000>;
310 ranges = <0x0 0x40300000 0x80000>;
324 sram-hs@0 {
326 reg = <0x0 0x0>;
339 reg = <0x40400000 0x100000>;
340 ranges = <0x0 0x40400000 0x100000>;
348 reg = <0x40500000 0x100000>;
349 ranges = <0x0 0x40500000 0x100000>;
355 reg = <0x4a0021e0 0xc
356 0x4a00232c 0xc
357 0x4a002380 0x2c
358 0x4a0023C0 0x3c
359 0x4a002564 0x8
360 0x4a002574 0x50>;
368 reg = <0x40d00000 0x100>;
373 reg = <0x4844a000 0x0d1c>;
375 #size-cells = <0>;
381 reg = <0x43300000 0x4>,
382 <0x43300010 0x4>;
390 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
394 ranges = <0x0 0x43300000 0x100000>;
396 edma: dma@0 {
398 reg = <0 0x100000>;
408 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
421 reg = <0x43400000 0x4>,
422 <0x43400010 0x4>;
430 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
434 ranges = <0x0 0x43400000 0x100000>;
436 edma_tptc0: dma@0 {
438 reg = <0 0x100000>;
446 reg = <0x43500000 0x4>,
447 <0x43500010 0x4>;
455 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
459 ranges = <0x0 0x43500000 0x100000>;
461 edma_tptc1: dma@0 {
463 reg = <0 0x100000>;
471 reg = <0x4e000000 0x4>,
472 <0x4e000010 0x4>;
477 ranges = <0x0 0x4e000000 0x2000000>;
481 dmm@0 {
483 reg = <0 0x800>;
490 reg = <0x58820000 0x10000>;
494 resets = <&prm_ipu 0>, <&prm_ipu 1>;
495 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
501 reg = <0x55020000 0x10000>;
505 resets = <&prm_core 0>, <&prm_core 1>;
506 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
512 reg = <0x40800000 0x48000>,
513 <0x40e00000 0x8000>,
514 <0x40f00000 0x8000>;
516 ti,bootreg = <&scm_conf 0x55c 10>;
519 resets = <&prm_dsp1 0>;
520 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
526 reg = <0x40d01000 0x4>,
527 <0x40d01010 0x4>,
528 <0x40d01014 0x4>;
536 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
540 ranges = <0x0 0x40d01000 0x1000>;
544 mmu0_dsp1: mmu@0 {
546 reg = <0x0 0x100>;
548 #iommu-cells = <0>;
549 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
555 reg = <0x40d02000 0x4>,
556 <0x40d02010 0x4>,
557 <0x40d02014 0x4>;
565 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
569 ranges = <0x0 0x40d02000 0x1000>;
573 mmu1_dsp1: mmu@0 {
575 reg = <0x0 0x100>;
577 #iommu-cells = <0>;
578 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
584 reg = <0x58882000 0x4>,
585 <0x58882010 0x4>,
586 <0x58882014 0x4>;
594 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
600 ranges = <0x0 0x58882000 0x100>;
602 mmu_ipu1: mmu@0 {
604 reg = <0x0 0x100>;
606 #iommu-cells = <0>;
613 reg = <0x55082000 0x4>,
614 <0x55082010 0x4>,
615 <0x55082014 0x4>;
623 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
629 ranges = <0x0 0x55082000 0x100>;
631 mmu_ipu2: mmu@0 {
633 reg = <0x0 0x100>;
635 #iommu-cells = <0>;
643 #address-cells = <0>;
644 #size-cells = <0>;
649 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
650 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
651 <0x4ae0c158 0x4>;
655 ti,tranxdone-status-mask = <0x80>;
657 ti,ldovbb-override-mask = <0x400>;
659 ti,ldovbb-vset-mask = <0x1F>;
667 1060000 0 0x0 0 0x02000000 0x01F00000
668 1160000 0 0x4 0 0x02000000 0x01F00000
669 1210000 0 0x8 0 0x02000000 0x01F00000
676 #address-cells = <0>;
677 #size-cells = <0>;
682 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
683 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
684 <0x4a002470 0x4>;
688 ti,tranxdone-status-mask = <0x40000000>;
690 ti,ldovbb-override-mask = <0x400>;
692 ti,ldovbb-vset-mask = <0x1F>;
700 1055000 0 0x0 0 0x02000000 0x01F00000
701 1150000 0 0x4 0 0x02000000 0x01F00000
702 1250000 0 0x8 0 0x02000000 0x01F00000
709 #address-cells = <0>;
710 #size-cells = <0>;
715 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
716 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
717 <0x4a00246c 0x4>;
721 ti,tranxdone-status-mask = <0x20000000>;
723 ti,ldovbb-override-mask = <0x400>;
725 ti,ldovbb-vset-mask = <0x1F>;
733 1055000 0 0x0 0 0x02000000 0x01F00000
734 1150000 0 0x4 0 0x02000000 0x01F00000
735 1250000 0 0x8 0 0x02000000 0x01F00000
742 #address-cells = <0>;
743 #size-cells = <0>;
748 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
749 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
750 <0x4ae0c154 0x4>;
754 ti,tranxdone-status-mask = <0x10000000>;
756 ti,ldovbb-override-mask = <0x400>;
758 ti,ldovbb-vset-mask = <0x1F>;
766 1090000 0 0x0 0 0x02000000 0x01F00000
767 1210000 0 0x4 0 0x02000000 0x01F00000
768 1280000 0 0x8 0 0x02000000 0x01F00000
774 reg = <0x4b300000 0x4>,
775 <0x4b300010 0x4>;
781 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>;
785 ranges = <0x0 0x4b300000 0x1000>,
786 <0x5c000000 0x5c000000 0x4000000>;
788 qspi: spi@0 {
790 reg = <0 0x100>,
791 <0x5c000000 0x4000000>;
793 syscon-chipselects = <&scm_conf 0x558>;
795 #size-cells = <0>;
809 reg = <0x50000000 4>,
810 <0x50000010 4>,
811 <0x50000014 4>;
817 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>;
821 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
822 <0x00000000 0x00000000 0x40000000>; /* data */
826 reg = <0x50000000 0x37c>; /* device IO registers */
828 dmas = <&edma_xbar 4 0>;
844 reg = <0x5600fe00 0x4>,
845 <0x5600fe10 0x4>;
854 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
858 ranges = <0 0x56000000 0x2000000>;
860 gpu@0 {
862 reg = <0x0 0x10000>; /* 64kB */
869 reg = <0x4a002a48 0x130>;
876 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
878 ti,irqs-safe-map = <0>;
883 reg = <0x58000000 4>,
884 <0x58000014 4>;
887 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>,
894 ranges = <0 0x58000000 0x800000>;
896 dss: dss@0 {
902 syscon-pll-ctrl = <&scm_conf 0x538>;
905 ranges = <0 0 0x800000>;
909 reg = <0x1000 0x4>,
910 <0x1010 0x4>,
911 <0x1014 0x4>;
928 ranges = <0 0x1000 0x1000>;
930 dispc@0 {
932 reg = <0 0x1000>;
937 syscon-pol = <&scm_conf 0x534>;
943 reg = <0x40000 0x4>,
944 <0x40010 0x4>;
956 ranges = <0 0x40000 0x40000>;
958 hdmi: encoder@0 {
960 reg = <0 0x200>,
961 <0x200 0x80>,
962 <0x300 0x80>,
963 <0x20000 0x19000>;
979 reg = <0x59000020 0x4>;
981 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
985 ranges = <0x0 0x59000000 0x1000>;
987 bb2d: gpu@0 {
989 reg = <0x0 0x700>;
991 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
998 reg = <0x4b500080 0x4>,
999 <0x4b500084 0x4>,
1000 <0x4b500088 0x4>;
1010 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
1014 ranges = <0x0 0x4b500000 0x1000>;
1016 aes1: aes@0 {
1018 reg = <0 0xa0>;
1020 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1029 reg = <0x4b700080 0x4>,
1030 <0x4b700084 0x4>,
1031 <0x4b700088 0x4>;
1041 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
1045 ranges = <0x0 0x4b700000 0x1000>;
1047 aes2: aes@0 {
1049 reg = <0 0xa0>;
1051 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1060 reg = <0x4b101100 0x4>,
1061 <0x4b101110 0x4>,
1062 <0x4b101114 0x4>;
1071 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
1075 ranges = <0x0 0x4b101000 0x1000>;
1077 sham1: sham@0 {
1079 reg = <0 0x300>;
1081 dmas = <&edma_xbar 119 0>;
1090 reg = <0x42701100 0x4>,
1091 <0x42701110 0x4>,
1092 <0x42701114 0x4>;
1101 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>;
1105 ranges = <0x0 0x42701000 0x1000>;
1107 sham2: sham@0 {
1109 reg = <0 0x300>;
1111 dmas = <&edma_xbar 165 0>;
1120 reg = <0x5a05a400 0x4>,
1121 <0x5a05a410 0x4>;
1132 clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>;
1136 ranges = <0x5a000000 0x5a000000 0x1000000>,
1137 <0x5b000000 0x5b000000 0x1000000>;
1146 reg = <0x4a003b20 0xc>;
1149 1060000 0x0
1150 1160000 0x4
1151 1210000 0x8
1170 coefficients = <0 2000>;
1174 coefficients = <0 2000>;
1178 coefficients = <0 2000>;
1182 coefficients = <0 2000>;
1186 coefficients = <0 2000>;
1215 reg = <0x300 0x100>;
1216 #power-domain-cells = <0>;
1221 reg = <0x400 0x100>;
1223 #power-domain-cells = <0>;
1228 reg = <0x500 0x100>;
1230 #power-domain-cells = <0>;
1235 reg = <0x628 0xd8>;
1236 #power-domain-cells = <0>;
1241 reg = <0x700 0x100>;
1243 #power-domain-cells = <0>;
1248 reg = <0xf00 0x100>;
1250 #power-domain-cells = <0>;
1255 reg = <0x1000 0x100>;
1256 #power-domain-cells = <0>;
1261 reg = <0x1100 0x100>;
1262 #power-domain-cells = <0>;
1267 reg = <0x1200 0x100>;
1268 #power-domain-cells = <0>;
1273 reg = <0x1300 0x100>;
1275 #power-domain-cells = <0>;
1280 reg = <0x1400 0x100>;
1281 #power-domain-cells = <0>;
1286 reg = <0x1600 0x100>;
1287 #power-domain-cells = <0>;
1292 reg = <0x1724 0x100>;
1293 #power-domain-cells = <0>;
1298 reg = <0x1b00 0x40>;
1300 #power-domain-cells = <0>;
1305 reg = <0x1b40 0x40>;
1306 #power-domain-cells = <0>;
1311 reg = <0x1b80 0x40>;
1312 #power-domain-cells = <0>;
1317 reg = <0x1bc0 0x40>;
1318 #power-domain-cells = <0>;
1323 reg = <0x1c00 0x60>;
1324 #power-domain-cells = <0>;
1329 reg = <0x1c60 0x20>;
1330 #power-domain-cells = <0>;
1335 reg = <0x1c80 0x80>;
1336 #power-domain-cells = <0>;
1344 timer@0 {
1354 timer@0 {
1363 timer@0 {