Lines Matching full:l4per2_clkctrl
2311 clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>;
2422 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2452 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2482 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2552 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2598 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2644 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2797 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2798 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2799 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2816 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2818 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2833 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2834 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2851 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2852 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2867 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2868 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2885 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2886 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2901 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2902 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2919 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2920 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2935 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2936 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2953 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2954 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2969 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2970 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2987 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2988 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
3003 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3004 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
3021 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
3022 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
3032 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;