Lines Matching +full:0 +full:xaa000
1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
22 <0x00000800 0x00000800 0x000800>, /* ap 1 */
23 <0x00001000 0x00001000 0x000400>, /* ap 2 */
24 <0x00001400 0x00001400 0x000400>; /* ap 3 */
27 segment@100000 { /* 0x44d00000 */
31 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
32 <0x00004000 0x00104000 0x001000>, /* ap 5 */
33 <0x00080000 0x00180000 0x002000>, /* ap 6 */
34 <0x00082000 0x00182000 0x001000>, /* ap 7 */
35 <0x000f0000 0x001f0000 0x010000>; /* ap 8 */
37 target-module@0 { /* 0x44d00000, ap 4 28.0 */
39 reg = <0x0 0x4>;
41 clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>;
45 ranges = <0x00000000 0x00000000 0x4000>,
46 <0x00080000 0x00080000 0x2000>;
48 wkup_m3: cpu@0 {
50 reg = <0x00000000 0x4000>,
51 <0x00080000 0x2000>;
59 target-module@f0000 { /* 0x44df0000, ap 8 58.0 */
61 reg = <0xf0000 0x4>;
65 ranges = <0x0 0xf0000 0x10000>;
67 prcm: prcm@0 {
69 reg = <0x0 0x11000>;
73 ranges = <0 0 0x11000>;
77 #size-cells = <0>;
86 segment@200000 { /* 0x44e00000 */
90 ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */
91 <0x00003000 0x00203000 0x001000>, /* ap 10 */
92 <0x00004000 0x00204000 0x001000>, /* ap 11 */
93 <0x00005000 0x00205000 0x001000>, /* ap 12 */
94 <0x00006000 0x00206000 0x001000>, /* ap 13 */
95 <0x00007000 0x00207000 0x001000>, /* ap 14 */
96 <0x00008000 0x00208000 0x001000>, /* ap 15 */
97 <0x00009000 0x00209000 0x001000>, /* ap 16 */
98 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */
99 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */
100 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */
101 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */
102 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */
103 <0x00010000 0x00210000 0x010000>, /* ap 22 */
104 <0x00030000 0x00230000 0x001000>, /* ap 23 */
105 <0x00031000 0x00231000 0x001000>, /* ap 24 */
106 <0x00032000 0x00232000 0x001000>, /* ap 25 */
107 <0x00033000 0x00233000 0x001000>, /* ap 26 */
108 <0x00034000 0x00234000 0x001000>, /* ap 27 */
109 <0x00035000 0x00235000 0x001000>, /* ap 28 */
110 <0x00036000 0x00236000 0x001000>, /* ap 29 */
111 <0x00037000 0x00237000 0x001000>, /* ap 30 */
112 <0x00038000 0x00238000 0x001000>, /* ap 31 */
113 <0x00039000 0x00239000 0x001000>, /* ap 32 */
114 <0x0003a000 0x0023a000 0x001000>, /* ap 33 */
115 <0x0003e000 0x0023e000 0x001000>, /* ap 34 */
116 <0x0003f000 0x0023f000 0x001000>, /* ap 35 */
117 <0x00040000 0x00240000 0x040000>, /* ap 36 */
118 <0x00080000 0x00280000 0x001000>, /* ap 37 */
119 <0x00088000 0x00288000 0x008000>, /* ap 38 */
120 <0x00092000 0x00292000 0x001000>, /* ap 39 */
121 <0x00086000 0x00286000 0x001000>, /* ap 40 */
122 <0x00087000 0x00287000 0x001000>, /* ap 41 */
123 <0x00090000 0x00290000 0x001000>, /* ap 42 */
124 <0x00091000 0x00291000 0x001000>; /* ap 43 */
126 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */
131 ranges = <0x0 0x3000 0x1000>;
134 target-module@5000 { /* 0x44e05000, ap 12 30.0 */
139 ranges = <0x0 0x5000 0x1000>;
142 target-module@7000 { /* 0x44e07000, ap 14 20.0 */
144 reg = <0x7000 0x4>,
145 <0x7010 0x4>,
146 <0x7114 0x4>;
157 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>,
162 ranges = <0x0 0x7000 0x1000>;
164 gpio0: gpio@0 {
166 reg = <0x0 0x1000>;
176 target-module@9000 { /* 0x44e09000, ap 16 04.0 */
178 reg = <0x9050 0x4>,
179 <0x9054 0x4>,
180 <0x9058 0x4>;
189 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>;
193 ranges = <0x0 0x9000 0x1000>;
195 uart0: serial@0 {
197 reg = <0x0 0x2000>;
202 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
204 reg = <0xb000 0x8>,
205 <0xb010 0x8>,
206 <0xb090 0x8>;
218 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>;
222 ranges = <0x0 0xb000 0x1000>;
224 i2c0: i2c@0 {
226 reg = <0x0 0x1000>;
229 #size-cells = <0>;
234 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
236 reg = <0xd000 0x4>,
237 <0xd010 0x4>;
244 clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>;
248 ranges = <0x0 0xd000 0x1000>;
250 tscadc: tscadc@0 {
252 reg = <0x0 0x1000>;
257 dmas = <&edma 53 0>, <&edma 57 0>;
272 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
274 reg = <0x10000 0x4>;
276 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_CONTROL_CLKCTRL 0>;
281 ranges = <0x0 0x10000 0x10000>;
283 scm: scm@0 {
285 reg = <0x0 0x4000>;
288 ranges = <0 0 0x4000>;
293 reg = <0x800 0x31c>;
295 #size-cells = <0>;
300 pinctrl-single,function-mask = <0xffffffff>;
303 scm_conf: scm_conf@0 {
305 reg = <0x0 0x800>;
311 reg = <0x650 0x4>;
317 #size-cells = <0>;
323 reg = <0x1324 0x44>;
331 reg = <0xf90 0x40>;
342 timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */
344 reg = <0x31000 0x4>,
345 <0x31010 0x4>,
346 <0x31014 0x4>;
356 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>;
360 ranges = <0x0 0x31000 0x1000>;
362 timer1: timer@0 {
364 reg = <0x0 0x400>;
372 target-module@33000 { /* 0x44e33000, ap 26 18.0 */
377 ranges = <0x0 0x33000 0x1000>;
380 target-module@35000 { /* 0x44e35000, ap 28 50.0 */
382 reg = <0x35000 0x4>,
383 <0x35010 0x4>,
384 <0x35014 0x4>;
394 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
398 ranges = <0x0 0x35000 0x1000>;
400 wdt: wdt@0 {
402 reg = <0x0 0x1000>;
407 target-module@37000 { /* 0x44e37000, ap 30 08.0 */
412 ranges = <0x0 0x37000 0x1000>;
415 target-module@39000 { /* 0x44e39000, ap 32 02.0 */
420 ranges = <0x0 0x39000 0x1000>;
423 rtc_target: target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */
425 reg = <0x3e074 0x4>,
426 <0x3e078 0x4>;
434 clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>;
438 ranges = <0x0 0x3e000 0x1000>;
440 rtc: rtc@0 {
443 reg = <0x0 0x1000>;
453 target-module@40000 { /* 0x44e40000, ap 36 68.0 */
458 ranges = <0x0 0x40000 0x40000>;
461 target-module@86000 { /* 0x44e86000, ap 40 70.0 */
463 reg = <0x86000 0x4>,
464 <0x86004 0x4>;
469 clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>;
473 ranges = <0x0 0x86000 0x1000>;
475 counter32k: counter@0 {
477 reg = <0x0 0x40>;
481 target-module@88000 { /* 0x44e88000, ap 38 12.0 */
486 ranges = <0x00000000 0x00088000 0x00008000>,
487 <0x00008000 0x00090000 0x00001000>,
488 <0x00009000 0x00091000 0x00001000>;
493 &l4_fast { /* 0x4a000000 */
496 clocks = <&l3_clkctrl AM4_L3_L4_HS_CLKCTRL 0>;
498 reg = <0x4a000000 0x800>,
499 <0x4a000800 0x800>,
500 <0x4a001000 0x400>;
504 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
506 segment@0 { /* 0x4a000000 */
510 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
511 <0x00000800 0x00000800 0x000800>, /* ap 1 */
512 <0x00001000 0x00001000 0x000400>, /* ap 2 */
513 <0x00100000 0x00100000 0x008000>, /* ap 3 */
514 <0x00108000 0x00108000 0x001000>, /* ap 4 */
515 <0x00400000 0x00400000 0x002000>, /* ap 5 */
516 <0x00402000 0x00402000 0x001000>, /* ap 6 */
517 <0x00200000 0x00200000 0x080000>, /* ap 7 */
518 <0x00280000 0x00280000 0x001000>; /* ap 8 */
520 target-module@100000 { /* 0x4a100000, ap 3 04.0 */
522 reg = <0x101200 0x4>,
523 <0x101208 0x4>,
524 <0x101204 0x4>;
526 ti,sysc-mask = <0>;
532 clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
536 ranges = <0x0 0x100000 0x8000>;
538 mac_sw: switch@0 {
540 reg = <0x0 0x4000>;
541 ranges = <0 0 0x4000>;
559 #size-cells = <0>;
565 phys = <&phy_gmii_sel 1 0>;
572 phys = <&phy_gmii_sel 2 0>;
581 #size-cells = <0>;
583 reg = <0x1000 0x100>;
593 target-module@200000 { /* 0x4a200000, ap 7 02.0 */
598 ranges = <0x0 0x200000 0x80000>;
601 target-module@400000 { /* 0x4a400000, ap 5 08.0 */
606 ranges = <0x0 0x400000 0x2000>;
611 &l4_per { /* 0x48000000 */
614 clocks = <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
616 reg = <0x48000000 0x800>,
617 <0x48000800 0x800>,
618 <0x48001000 0x400>,
619 <0x48001400 0x400>,
620 <0x48001800 0x400>,
621 <0x48001c00 0x400>;
625 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
626 <0x00100000 0x48100000 0x100000>, /* segment 1 */
627 <0x00200000 0x48200000 0x100000>, /* segment 2 */
628 <0x00300000 0x48300000 0x100000>, /* segment 3 */
629 <0x46000000 0x46000000 0x400000>, /* l3 data port */
630 <0x46400000 0x46400000 0x400000>; /* l3 data port */
632 segment@0 { /* 0x48000000 */
636 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
637 <0x00000800 0x00000800 0x000800>, /* ap 1 */
638 <0x00001000 0x00001000 0x000400>, /* ap 2 */
639 <0x00001400 0x00001400 0x000400>, /* ap 3 */
640 <0x00001800 0x00001800 0x000400>, /* ap 4 */
641 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */
642 <0x00008000 0x00008000 0x001000>, /* ap 6 */
643 <0x00009000 0x00009000 0x001000>, /* ap 7 */
644 <0x00022000 0x00022000 0x001000>, /* ap 8 */
645 <0x00023000 0x00023000 0x001000>, /* ap 9 */
646 <0x00024000 0x00024000 0x001000>, /* ap 10 */
647 <0x00025000 0x00025000 0x001000>, /* ap 11 */
648 <0x0002a000 0x0002a000 0x001000>, /* ap 12 */
649 <0x0002b000 0x0002b000 0x001000>, /* ap 13 */
650 <0x00038000 0x00038000 0x002000>, /* ap 14 */
651 <0x0003a000 0x0003a000 0x001000>, /* ap 15 */
652 <0x0003c000 0x0003c000 0x002000>, /* ap 16 */
653 <0x0003e000 0x0003e000 0x001000>, /* ap 17 */
654 <0x00040000 0x00040000 0x001000>, /* ap 18 */
655 <0x00041000 0x00041000 0x001000>, /* ap 19 */
656 <0x00042000 0x00042000 0x001000>, /* ap 20 */
657 <0x00043000 0x00043000 0x001000>, /* ap 21 */
658 <0x00044000 0x00044000 0x001000>, /* ap 22 */
659 <0x00045000 0x00045000 0x001000>, /* ap 23 */
660 <0x00046000 0x00046000 0x001000>, /* ap 24 */
661 <0x00047000 0x00047000 0x001000>, /* ap 25 */
662 <0x00048000 0x00048000 0x001000>, /* ap 26 */
663 <0x00049000 0x00049000 0x001000>, /* ap 27 */
664 <0x0004c000 0x0004c000 0x001000>, /* ap 28 */
665 <0x0004d000 0x0004d000 0x001000>, /* ap 29 */
666 <0x00060000 0x00060000 0x001000>, /* ap 30 */
667 <0x00061000 0x00061000 0x001000>, /* ap 31 */
668 <0x00080000 0x00080000 0x010000>, /* ap 32 */
669 <0x00090000 0x00090000 0x001000>, /* ap 33 */
670 <0x00030000 0x00030000 0x001000>, /* ap 65 */
671 <0x00031000 0x00031000 0x001000>, /* ap 66 */
672 <0x0004a000 0x0004a000 0x001000>, /* ap 71 */
673 <0x0004b000 0x0004b000 0x001000>, /* ap 72 */
674 <0x000c8000 0x000c8000 0x001000>, /* ap 73 */
675 <0x000c9000 0x000c9000 0x001000>, /* ap 74 */
676 <0x000ca000 0x000ca000 0x001000>, /* ap 77 */
677 <0x000cb000 0x000cb000 0x001000>, /* ap 78 */
678 <0x00034000 0x00034000 0x001000>, /* ap 80 */
679 <0x00035000 0x00035000 0x001000>, /* ap 81 */
680 <0x00036000 0x00036000 0x001000>, /* ap 84 */
681 <0x00037000 0x00037000 0x001000>, /* ap 85 */
682 <0x46000000 0x46000000 0x400000>, /* l3 data port */
683 <0x46400000 0x46400000 0x400000>; /* l3 data port */
685 target-module@8000 { /* 0x48008000, ap 6 10.0 */
690 ranges = <0x0 0x8000 0x1000>;
693 target-module@22000 { /* 0x48022000, ap 8 0a.0 */
695 reg = <0x22050 0x4>,
696 <0x22054 0x4>,
697 <0x22058 0x4>;
706 clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>;
710 ranges = <0x0 0x22000 0x1000>;
712 uart1: serial@0 {
714 reg = <0x0 0x2000>;
720 target-module@24000 { /* 0x48024000, ap 10 1c.0 */
722 reg = <0x24050 0x4>,
723 <0x24054 0x4>,
724 <0x24058 0x4>;
733 clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>;
737 ranges = <0x0 0x24000 0x1000>;
739 uart2: serial@0 {
741 reg = <0x0 0x2000>;
747 target-module@2a000 { /* 0x4802a000, ap 12 22.0 */
749 reg = <0x2a000 0x8>,
750 <0x2a010 0x8>,
751 <0x2a090 0x8>;
763 clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>;
767 ranges = <0x0 0x2a000 0x1000>;
769 i2c1: i2c@0 {
771 reg = <0x0 0x1000>;
774 #size-cells = <0>;
779 target-module@30000 { /* 0x48030000, ap 65 08.0 */
781 reg = <0x30000 0x4>,
782 <0x30110 0x4>,
783 <0x30114 0x4>;
793 clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>;
797 ranges = <0x0 0x30000 0x1000>;
799 spi0: spi@0 {
801 reg = <0x0 0x400>;
804 #size-cells = <0>;
809 target-module@34000 { /* 0x48034000, ap 80 56.0 */
814 ranges = <0x0 0x34000 0x1000>;
817 target-module@36000 { /* 0x48036000, ap 84 3e.0 */
822 ranges = <0x0 0x36000 0x1000>;
825 target-module@38000 { /* 0x48038000, ap 14 04.0 */
827 reg = <0x38000 0x4>,
828 <0x38004 0x4>;
834 clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>;
838 ranges = <0x0 0x38000 0x2000>,
839 <0x46000000 0x46000000 0x400000>;
841 mcasp0: mcasp@0 {
843 reg = <0x0 0x2000>,
844 <0x46000000 0x400000>;
856 target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */
858 reg = <0x3c000 0x4>,
859 <0x3c004 0x4>;
865 clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>;
869 ranges = <0x0 0x3c000 0x2000>,
870 <0x46400000 0x46400000 0x400000>;
872 mcasp1: mcasp@0 {
874 reg = <0x0 0x2000>,
875 <0x46400000 0x400000>;
887 timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */
889 reg = <0x40000 0x4>,
890 <0x40010 0x4>,
891 <0x40014 0x4>;
899 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>;
903 ranges = <0x0 0x40000 0x1000>;
905 timer2: timer@0 {
907 reg = <0x0 0x400>;
914 target-module@42000 { /* 0x48042000, ap 20 24.0 */
916 reg = <0x42000 0x4>,
917 <0x42010 0x4>,
918 <0x42014 0x4>;
926 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>;
930 ranges = <0x0 0x42000 0x1000>;
932 timer3: timer@0 {
934 reg = <0x0 0x400>;
940 target-module@44000 { /* 0x48044000, ap 22 26.0 */
942 reg = <0x44000 0x4>,
943 <0x44010 0x4>,
944 <0x44014 0x4>;
952 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>;
956 ranges = <0x0 0x44000 0x1000>;
958 timer4: timer@0 {
960 reg = <0x0 0x400>;
967 target-module@46000 { /* 0x48046000, ap 24 28.0 */
969 reg = <0x46000 0x4>,
970 <0x46010 0x4>,
971 <0x46014 0x4>;
979 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>;
983 ranges = <0x0 0x46000 0x1000>;
985 timer5: timer@0 {
987 reg = <0x0 0x400>;
994 target-module@48000 { /* 0x48048000, ap 26 1a.0 */
996 reg = <0x48000 0x4>,
997 <0x48010 0x4>,
998 <0x48014 0x4>;
1006 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>;
1010 ranges = <0x0 0x48000 0x1000>;
1012 timer6: timer@0 {
1014 reg = <0x0 0x400>;
1021 target-module@4a000 { /* 0x4804a000, ap 71 48.0 */
1023 reg = <0x4a000 0x4>,
1024 <0x4a010 0x4>,
1025 <0x4a014 0x4>;
1033 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>;
1037 ranges = <0x0 0x4a000 0x1000>;
1039 timer7: timer@0 {
1041 reg = <0x0 0x400>;
1048 target-module@4c000 { /* 0x4804c000, ap 28 36.0 */
1050 reg = <0x4c000 0x4>,
1051 <0x4c010 0x4>,
1052 <0x4c114 0x4>;
1063 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>,
1068 ranges = <0x0 0x4c000 0x1000>;
1070 gpio1: gpio@0 {
1072 reg = <0x0 0x1000>;
1082 target-module@60000 { /* 0x48060000, ap 30 14.0 */
1084 reg = <0x602fc 0x4>,
1085 <0x60110 0x4>,
1086 <0x60114 0x4>;
1097 clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>;
1101 ranges = <0x0 0x60000 0x1000>;
1103 mmc1: mmc@0 {
1105 reg = <0x0 0x1000>;
1107 dmas = <&edma 24 0>,
1108 <&edma 25 0>;
1115 target-module@80000 { /* 0x48080000, ap 32 18.0 */
1117 reg = <0x80000 0x4>,
1118 <0x80010 0x4>,
1119 <0x80014 0x4>;
1129 clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>;
1133 ranges = <0x0 0x80000 0x10000>;
1135 elm: elm@0 {
1137 reg = <0x0 0x2000>;
1145 target-module@c8000 { /* 0x480c8000, ap 73 06.0 */
1147 reg = <0xc8000 0x4>,
1148 <0xc8010 0x4>;
1155 clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>;
1159 ranges = <0x0 0xc8000 0x1000>;
1161 mailbox: mailbox@0 {
1163 reg = <0x0 0x200>;
1170 ti,mbox-tx = <0 0 0>;
1171 ti,mbox-rx = <0 0 3>;
1176 target-module@ca000 { /* 0x480ca000, ap 77 38.0 */
1178 reg = <0xca000 0x4>,
1179 <0xca010 0x4>,
1180 <0xca014 0x4>;
1191 clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>;
1195 ranges = <0x0 0xca000 0x1000>;
1197 hwspinlock: spinlock@0 {
1199 reg = <0x0 0x1000>;
1205 segment@100000 { /* 0x48100000 */
1209 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */
1210 <0x0008d000 0x0018d000 0x001000>, /* ap 35 */
1211 <0x0008e000 0x0018e000 0x001000>, /* ap 36 */
1212 <0x0008f000 0x0018f000 0x001000>, /* ap 37 */
1213 <0x0009c000 0x0019c000 0x001000>, /* ap 38 */
1214 <0x0009d000 0x0019d000 0x001000>, /* ap 39 */
1215 <0x000a6000 0x001a6000 0x001000>, /* ap 40 */
1216 <0x000a7000 0x001a7000 0x001000>, /* ap 41 */
1217 <0x000a8000 0x001a8000 0x001000>, /* ap 42 */
1218 <0x000a9000 0x001a9000 0x001000>, /* ap 43 */
1219 <0x000aa000 0x001aa000 0x001000>, /* ap 44 */
1220 <0x000ab000 0x001ab000 0x001000>, /* ap 45 */
1221 <0x000ac000 0x001ac000 0x001000>, /* ap 46 */
1222 <0x000ad000 0x001ad000 0x001000>, /* ap 47 */
1223 <0x000ae000 0x001ae000 0x001000>, /* ap 48 */
1224 <0x000af000 0x001af000 0x001000>, /* ap 49 */
1225 <0x000cc000 0x001cc000 0x002000>, /* ap 50 */
1226 <0x000ce000 0x001ce000 0x002000>, /* ap 51 */
1227 <0x000d0000 0x001d0000 0x002000>, /* ap 52 */
1228 <0x000d2000 0x001d2000 0x002000>, /* ap 53 */
1229 <0x000d8000 0x001d8000 0x001000>, /* ap 54 */
1230 <0x000d9000 0x001d9000 0x001000>, /* ap 55 */
1231 <0x000a0000 0x001a0000 0x001000>, /* ap 67 */
1232 <0x000a1000 0x001a1000 0x001000>, /* ap 68 */
1233 <0x000a2000 0x001a2000 0x001000>, /* ap 69 */
1234 <0x000a3000 0x001a3000 0x001000>, /* ap 70 */
1235 <0x000a4000 0x001a4000 0x001000>, /* ap 92 */
1236 <0x000a5000 0x001a5000 0x001000>, /* ap 93 */
1237 <0x000c1000 0x001c1000 0x001000>, /* ap 94 */
1238 <0x000c2000 0x001c2000 0x001000>; /* ap 95 */
1240 target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */
1245 ranges = <0x0 0x8c000 0x1000>;
1248 target-module@8e000 { /* 0x4818e000, ap 36 02.0 */
1253 ranges = <0x0 0x8e000 0x1000>;
1256 target-module@9c000 { /* 0x4819c000, ap 38 52.0 */
1258 reg = <0x9c000 0x8>,
1259 <0x9c010 0x8>,
1260 <0x9c090 0x8>;
1272 clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>;
1276 ranges = <0x0 0x9c000 0x1000>;
1278 i2c2: i2c@0 {
1280 reg = <0x0 0x1000>;
1283 #size-cells = <0>;
1288 target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */
1290 reg = <0xa0000 0x4>,
1291 <0xa0110 0x4>,
1292 <0xa0114 0x4>;
1302 clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>;
1306 ranges = <0x0 0xa0000 0x1000>;
1308 spi1: spi@0 {
1310 reg = <0x0 0x400>;
1313 #size-cells = <0>;
1318 target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */
1320 reg = <0xa2000 0x4>,
1321 <0xa2110 0x4>,
1322 <0xa2114 0x4>;
1332 clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>;
1336 ranges = <0x0 0xa2000 0x1000>;
1338 spi2: spi@0 {
1340 reg = <0x0 0x400>;
1343 #size-cells = <0>;
1348 target-module@a4000 { /* 0x481a4000, ap 92 62.0 */
1350 reg = <0xa4000 0x4>,
1351 <0xa4110 0x4>,
1352 <0xa4114 0x4>;
1362 clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>;
1366 ranges = <0x0 0xa4000 0x1000>;
1368 spi3: spi@0 {
1370 reg = <0x0 0x400>;
1373 #size-cells = <0>;
1378 target-module@a6000 { /* 0x481a6000, ap 40 16.0 */
1380 reg = <0xa6050 0x4>,
1381 <0xa6054 0x4>,
1382 <0xa6058 0x4>;
1391 clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>;
1395 ranges = <0x0 0xa6000 0x1000>;
1397 uart3: serial@0 {
1399 reg = <0x0 0x2000>;
1405 target-module@a8000 { /* 0x481a8000, ap 42 20.0 */
1407 reg = <0xa8050 0x4>,
1408 <0xa8054 0x4>,
1409 <0xa8058 0x4>;
1418 clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>;
1422 ranges = <0x0 0xa8000 0x1000>;
1424 uart4: serial@0 {
1426 reg = <0x0 0x2000>;
1432 target-module@aa000 { /* 0x481aa000, ap 44 12.0 */
1434 reg = <0xaa050 0x4>,
1435 <0xaa054 0x4>,
1436 <0xaa058 0x4>;
1445 clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>;
1449 ranges = <0x0 0xaa000 0x1000>;
1451 uart5: serial@0 {
1453 reg = <0x0 0x2000>;
1459 target-module@ac000 { /* 0x481ac000, ap 46 30.0 */
1461 reg = <0xac000 0x4>,
1462 <0xac010 0x4>,
1463 <0xac114 0x4>;
1474 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>,
1479 ranges = <0x0 0xac000 0x1000>;
1481 gpio2: gpio@0 {
1483 reg = <0x0 0x1000>;
1493 target-module@ae000 { /* 0x481ae000, ap 48 32.0 */
1495 reg = <0xae000 0x4>,
1496 <0xae010 0x4>,
1497 <0xae114 0x4>;
1508 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>,
1513 ranges = <0x0 0xae000 0x1000>;
1515 gpio3: gpio@0 {
1517 reg = <0x0 0x1000>;
1527 target-module@c1000 { /* 0x481c1000, ap 94 68.0 */
1529 reg = <0xc1000 0x4>,
1530 <0xc1010 0x4>,
1531 <0xc1014 0x4>;
1539 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>;
1543 ranges = <0x0 0xc1000 0x1000>;
1545 timer8: timer@0 {
1547 reg = <0x0 0x400>;
1553 target-module@cc000 { /* 0x481cc000, ap 50 46.0 */
1555 reg = <0xcc020 0x4>;
1558 clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>,
1563 ranges = <0x0 0xcc000 0x2000>;
1565 dcan0: can@0 {
1567 reg = <0x0 0x2000>;
1570 syscon-raminit = <&scm_conf 0x644 0>;
1576 target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */
1578 reg = <0xd0020 0x4>;
1581 clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>,
1586 ranges = <0x0 0xd0000 0x2000>;
1588 dcan1: can@0 {
1590 reg = <0x0 0x2000>;
1593 syscon-raminit = <&scm_conf 0x644 1>;
1599 target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */
1601 reg = <0xd82fc 0x4>,
1602 <0xd8110 0x4>,
1603 <0xd8114 0x4>;
1614 clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>;
1618 ranges = <0x0 0xd8000 0x1000>;
1620 mmc2: mmc@0 {
1622 reg = <0x0 0x1000>;
1624 dmas = <&edma 2 0>,
1625 <&edma 3 0>;
1633 segment@200000 { /* 0x48200000 */
1637 ranges = <0x00000000 0x00200000 0x010000>;
1639 target-module@0 {
1642 clocks = <&mpu_clkctrl AM4_MPU_MPU_CLKCTRL 0>;
1647 ranges = <0 0 0x10000>;
1649 mpu@0 {
1657 segment@300000 { /* 0x48300000 */
1661 ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */
1662 <0x00001000 0x00301000 0x001000>, /* ap 57 */
1663 <0x00002000 0x00302000 0x001000>, /* ap 58 */
1664 <0x00003000 0x00303000 0x001000>, /* ap 59 */
1665 <0x00004000 0x00304000 0x001000>, /* ap 60 */
1666 <0x00005000 0x00305000 0x001000>, /* ap 61 */
1667 <0x00018000 0x00318000 0x004000>, /* ap 62 */
1668 <0x0001c000 0x0031c000 0x001000>, /* ap 63 */
1669 <0x00010000 0x00310000 0x002000>, /* ap 64 */
1670 <0x00028000 0x00328000 0x001000>, /* ap 75 */
1671 <0x00029000 0x00329000 0x001000>, /* ap 76 */
1672 <0x00012000 0x00312000 0x001000>, /* ap 79 */
1673 <0x00020000 0x00320000 0x001000>, /* ap 82 */
1674 <0x00021000 0x00321000 0x001000>, /* ap 83 */
1675 <0x00026000 0x00326000 0x001000>, /* ap 86 */
1676 <0x00027000 0x00327000 0x001000>, /* ap 87 */
1677 <0x0002a000 0x0032a000 0x000400>, /* ap 88 */
1678 <0x0002c000 0x0032c000 0x001000>, /* ap 89 */
1679 <0x00013000 0x00313000 0x001000>, /* ap 90 */
1680 <0x00014000 0x00314000 0x001000>, /* ap 91 */
1681 <0x00006000 0x00306000 0x001000>, /* ap 96 */
1682 <0x00007000 0x00307000 0x001000>, /* ap 97 */
1683 <0x00008000 0x00308000 0x001000>, /* ap 98 */
1684 <0x00009000 0x00309000 0x001000>, /* ap 99 */
1685 <0x0000a000 0x0030a000 0x001000>, /* ap 100 */
1686 <0x0000b000 0x0030b000 0x001000>, /* ap 101 */
1687 <0x0003d000 0x0033d000 0x001000>, /* ap 102 */
1688 <0x0003e000 0x0033e000 0x001000>, /* ap 103 */
1689 <0x0003f000 0x0033f000 0x001000>, /* ap 104 */
1690 <0x00040000 0x00340000 0x001000>, /* ap 105 */
1691 <0x00041000 0x00341000 0x001000>, /* ap 106 */
1692 <0x00042000 0x00342000 0x001000>, /* ap 107 */
1693 <0x00045000 0x00345000 0x001000>, /* ap 108 */
1694 <0x00046000 0x00346000 0x001000>, /* ap 109 */
1695 <0x00047000 0x00347000 0x001000>, /* ap 110 */
1696 <0x00048000 0x00348000 0x001000>, /* ap 111 */
1697 <0x000f2000 0x003f2000 0x002000>, /* ap 112 */
1698 <0x000f4000 0x003f4000 0x001000>, /* ap 113 */
1699 <0x0004c000 0x0034c000 0x002000>, /* ap 114 */
1700 <0x0004e000 0x0034e000 0x001000>, /* ap 115 */
1701 <0x00022000 0x00322000 0x001000>, /* ap 116 */
1702 <0x00023000 0x00323000 0x001000>, /* ap 117 */
1703 <0x000f0000 0x003f0000 0x001000>, /* ap 118 */
1704 <0x0002a400 0x0032a400 0x000400>, /* ap 119 */
1705 <0x0002a800 0x0032a800 0x000400>, /* ap 120 */
1706 <0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */
1707 <0x0002b000 0x0032b000 0x001000>, /* ap 122 */
1708 <0x00080000 0x00380000 0x020000>, /* ap 123 */
1709 <0x000a0000 0x003a0000 0x001000>, /* ap 124 */
1710 <0x000a8000 0x003a8000 0x008000>, /* ap 125 */
1711 <0x000b0000 0x003b0000 0x001000>, /* ap 126 */
1712 <0x000c0000 0x003c0000 0x020000>, /* ap 127 */
1713 <0x000e0000 0x003e0000 0x001000>, /* ap 128 */
1714 <0x000e8000 0x003e8000 0x008000>; /* ap 129 */
1716 target-module@0 { /* 0x48300000, ap 56 40.0 */
1718 reg = <0x0 0x4>,
1719 <0x4 0x4>;
1730 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>;
1734 ranges = <0x0 0x0 0x1000>;
1736 epwmss0: epwmss@0 {
1738 reg = <0x0 0x10>;
1741 ranges = <0 0 0x1000>;
1748 reg = <0x100 0x80>;
1758 reg = <0x200 0x80>;
1766 target-module@2000 { /* 0x48302000, ap 58 4a.0 */
1768 reg = <0x2000 0x4>,
1769 <0x2004 0x4>;
1780 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>;
1784 ranges = <0x0 0x2000 0x1000>;
1786 epwmss1: epwmss@0 {
1788 reg = <0x0 0x10>;
1791 ranges = <0 0 0x1000>;
1798 reg = <0x100 0x80>;
1808 reg = <0x200 0x80>;
1816 target-module@4000 { /* 0x48304000, ap 60 44.0 */
1818 reg = <0x4000 0x4>,
1819 <0x4004 0x4>;
1830 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>;
1834 ranges = <0x0 0x4000 0x1000>;
1836 epwmss2: epwmss@0 {
1838 reg = <0x0 0x10>;
1841 ranges = <0 0 0x1000>;
1848 reg = <0x100 0x80>;
1858 reg = <0x200 0x80>;
1866 target-module@6000 { /* 0x48306000, ap 96 58.0 */
1868 reg = <0x6000 0x4>,
1869 <0x6004 0x4>;
1880 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>;
1884 ranges = <0x0 0x6000 0x1000>;
1886 epwmss3: epwmss@0 {
1888 reg = <0x0 0x10>;
1891 ranges = <0 0 0x1000>;
1898 reg = <0x200 0x80>;
1906 target-module@8000 { /* 0x48308000, ap 98 54.0 */
1908 reg = <0x8000 0x4>,
1909 <0x8004 0x4>;
1920 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>;
1924 ranges = <0x0 0x8000 0x1000>;
1926 epwmss4: epwmss@0 {
1928 reg = <0x0 0x10>;
1931 ranges = <0 0 0x1000>;
1938 reg = <0x200 0x80>;
1946 target-module@a000 { /* 0x4830a000, ap 100 60.0 */
1948 reg = <0xa000 0x4>,
1949 <0xa004 0x4>;
1960 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>;
1964 ranges = <0x0 0xa000 0x1000>;
1966 epwmss5: epwmss@0 {
1968 reg = <0x0 0x10>;
1971 ranges = <0 0 0x1000>;
1978 reg = <0x200 0x80>;
1986 target-module@10000 { /* 0x48310000, ap 64 4e.1 */
1988 reg = <0x11fe0 0x4>,
1989 <0x11fe4 0x4>;
1995 clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>;
1999 ranges = <0x0 0x10000 0x2000>;
2001 rng: rng@0 {
2003 reg = <0x0 0x2000>;
2008 target-module@13000 { /* 0x48313000, ap 90 50.0 */
2013 ranges = <0x0 0x13000 0x1000>;
2016 target-module@18000 { /* 0x48318000, ap 62 4c.0 */
2021 ranges = <0x0 0x18000 0x4000>;
2024 target-module@20000 { /* 0x48320000, ap 82 34.0 */
2026 reg = <0x20000 0x4>,
2027 <0x20010 0x4>,
2028 <0x20114 0x4>;
2039 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>,
2044 ranges = <0x0 0x20000 0x1000>;
2046 gpio4: gpio@0 {
2048 reg = <0x0 0x1000>;
2058 gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */
2060 reg = <0x22000 0x4>,
2061 <0x22010 0x4>,
2062 <0x22114 0x4>;
2073 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>,
2078 ranges = <0x0 0x22000 0x1000>;
2080 gpio5: gpio@0 {
2082 reg = <0x0 0x1000>;
2092 target-module@26000 { /* 0x48326000, ap 86 66.0 */
2094 reg = <0x26000 0x4>,
2095 <0x26104 0x4>;
2104 clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>;
2108 ranges = <0x0 0x26000 0x1000>;
2110 vpfe0: vpfe@0 {
2112 reg = <0x0 0x2000>;
2118 target-module@28000 { /* 0x48328000, ap 75 0e.0 */
2120 reg = <0x28000 0x4>,
2121 <0x28104 0x4>;
2130 clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>;
2134 ranges = <0x0 0x28000 0x1000>;
2136 vpfe1: vpfe@0 {
2138 reg = <0x0 0x2000>;
2144 target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
2146 reg = <0x2a000 0x4>,
2147 <0x2a010 0x4>,
2148 <0x2a014 0x4>;
2154 clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
2158 ranges = <0x00000000 0x0002a000 0x00000400>,
2159 <0x00000400 0x0002a400 0x00000400>,
2160 <0x00000800 0x0002a800 0x00000400>,
2161 <0x00000c00 0x0002ac00 0x00000400>,
2162 <0x00001000 0x0002b000 0x00001000>;
2164 dss: dss@0 {
2166 reg = <0 0x200>;
2172 ranges = <0x00000000 0x00000000 0x00000400>,
2173 <0x00000400 0x00000400 0x00000400>,
2174 <0x00000800 0x00000800 0x00000400>,
2175 <0x00000c00 0x00000c00 0x00000400>,
2176 <0x00001000 0x00001000 0x00001000>;
2180 reg = <0x400 0x4>,
2181 <0x410 0x4>,
2182 <0x414 0x4>;
2195 clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
2199 ranges = <0 0x400 0x400>;
2201 dispc: dispc@0 {
2203 reg = <0 0x400>;
2214 reg = <0x800 0x4>,
2215 <0x810 0x4>,
2216 <0x814 0x4>;
2224 clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
2228 ranges = <0 0x800 0x400>;
2230 rfbi: rfbi@0 {
2232 reg = <0 0x100>;
2233 clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
2241 target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
2243 reg = <0x3d000 0x4>,
2244 <0x3d010 0x4>,
2245 <0x3d014 0x4>;
2253 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>;
2257 ranges = <0x0 0x3d000 0x1000>;
2259 timer9: timer@0 {
2261 reg = <0x0 0x400>;
2267 target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */
2269 reg = <0x3f000 0x4>,
2270 <0x3f010 0x4>,
2271 <0x3f014 0x4>;
2279 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>;
2283 ranges = <0x0 0x3f000 0x1000>;
2285 timer10: timer@0 {
2287 reg = <0x0 0x400>;
2293 target-module@41000 { /* 0x48341000, ap 106 76.0 */
2295 reg = <0x41000 0x4>,
2296 <0x41010 0x4>,
2297 <0x41014 0x4>;
2305 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>;
2309 ranges = <0x0 0x41000 0x1000>;
2311 timer11: timer@0 {
2313 reg = <0x0 0x400>;
2319 target-module@45000 { /* 0x48345000, ap 108 6a.0 */
2321 reg = <0x45000 0x4>,
2322 <0x45110 0x4>,
2323 <0x45114 0x4>;
2333 clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>;
2337 ranges = <0x0 0x45000 0x1000>;
2339 spi4: spi@0 {
2341 reg = <0x0 0x400>;
2344 #size-cells = <0>;
2349 target-module@47000 { /* 0x48347000, ap 110 70.0 */
2351 reg = <0x47000 0x4>,
2352 <0x47014 0x4>,
2353 <0x47018 0x4>;
2358 clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>;
2362 ranges = <0x0 0x47000 0x1000>;
2364 hdq: hdq@0 {
2366 reg = <0x0 0x1000>;
2374 target-module@4c000 { /* 0x4834c000, ap 114 72.0 */
2376 reg = <0x4c000 0x4>,
2377 <0x4c010 0x4>;
2382 clocks = <&l3s_clkctrl AM4_L3S_ADC1_CLKCTRL 0>;
2386 ranges = <0x0 0x4c000 0x2000>;
2388 magadc: magadc@0 {
2390 reg = <0x0 0x2000>;
2394 dmas = <&edma 54 0>, <&edma 55 0>;
2409 target-module@80000 { /* 0x48380000, ap 123 42.0 */
2411 reg = <0x80000 0x4>,
2412 <0x80010 0x4>;
2424 clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>;
2428 ranges = <0x0 0x80000 0x20000>;
2430 dwc3_1: omap_dwc3@0 {
2432 reg = <0x0 0x10000>;
2437 ranges = <0 0 0x20000>;
2441 reg = <0x10000 0x10000>;
2459 target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */
2461 reg = <0xa8000 0x4>;
2464 clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>;
2468 ranges = <0x0 0xa8000 0x8000>;
2470 ocp2scp0: ocp2scp@0 {
2474 ranges = <0 0 0x8000>;
2478 reg = <0x0 0x8000>;
2479 syscon-phy-power = <&scm_conf 0x620>;
2483 #phy-cells = <0>;
2489 target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */
2491 reg = <0xc0000 0x4>,
2492 <0xc0010 0x4>;
2504 clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>;
2508 ranges = <0x0 0xc0000 0x20000>;
2510 dwc3_2: omap_dwc3@0 {
2512 reg = <0x0 0x10000>;
2517 ranges = <0 0 0x20000>;
2521 reg = <0x10000 0x10000>;
2539 target-module@e8000 { /* 0x483e8000, ap 129 78.0 */
2541 reg = <0xe8000 0x4>;
2544 clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>;
2548 ranges = <0x0 0xe8000 0x8000>;
2550 ocp2scp1: ocp2scp@0 {
2554 ranges = <0 0 0x8000>;
2558 reg = <0x0 0x8000>;
2559 syscon-phy-power = <&scm_conf 0x628>;
2563 #phy-cells = <0>;
2569 target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */
2574 ranges = <0x0 0xf2000 0x2000>;