Lines Matching +full:1 +full:- +full:9 +full:a +full:- +full:d
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 /omit-if-no-ref/
10 adc1_ain_pins_a: adc1-ain-0 {
13 <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */
17 <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1_INP15 */
21 /omit-if-no-ref/
22 adc1_in6_pins_a: adc1-in6-0 {
28 /omit-if-no-ref/
29 adc12_ain_pins_a: adc12-ain-0 {
38 /omit-if-no-ref/
39 adc12_ain_pins_b: adc12-ain-1 {
46 /omit-if-no-ref/
47 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
49 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
50 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
54 /omit-if-no-ref/
55 cec_pins_a: cec-0 {
57 pinmux = <STM32_PINMUX('A', 15, AF4)>;
58 bias-disable;
59 drive-open-drain;
60 slew-rate = <0>;
64 /omit-if-no-ref/
65 cec_sleep_pins_a: cec-sleep-0 {
67 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
71 /omit-if-no-ref/
72 cec_pins_b: cec-1 {
75 bias-disable;
76 drive-open-drain;
77 slew-rate = <0>;
81 /omit-if-no-ref/
82 cec_sleep_pins_b: cec-sleep-1 {
88 /omit-if-no-ref/
89 dac_ch1_pins_a: dac-ch1-0 {
91 pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
95 /omit-if-no-ref/
96 dac_ch2_pins_a: dac-ch2-0 {
98 pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
102 /omit-if-no-ref/
103 dcmi_pins_a: dcmi-0 {
107 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
108 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
116 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
120 bias-disable;
124 /omit-if-no-ref/
125 dcmi_sleep_pins_a: dcmi-sleep-0 {
129 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
130 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
138 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
145 /omit-if-no-ref/
146 dcmi_pins_b: dcmi-1 {
148 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
150 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
154 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
156 <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
158 <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
159 bias-disable;
163 /omit-if-no-ref/
164 dcmi_sleep_pins_b: dcmi-sleep-1 {
166 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
168 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
172 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
174 <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
176 <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
180 /omit-if-no-ref/
181 dcmi_pins_c: dcmi-2 {
183 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
185 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
186 <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
189 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
194 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
196 bias-pull-up;
200 /omit-if-no-ref/
201 dcmi_sleep_pins_c: dcmi-sleep-2 {
203 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
205 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
206 <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
209 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
214 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
219 /omit-if-no-ref/
220 ethernet0_rgmii_pins_a: rgmii-0 {
229 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
230 bias-disable;
231 drive-push-pull;
232 slew-rate = <2>;
235 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
236 bias-disable;
237 drive-push-pull;
238 slew-rate = <0>;
244 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
245 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
246 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
247 bias-disable;
251 /omit-if-no-ref/
252 ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
261 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
262 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
266 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
267 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
268 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
272 /omit-if-no-ref/
273 ethernet0_rgmii_pins_b: rgmii-1 {
282 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
283 bias-disable;
284 drive-push-pull;
285 slew-rate = <2>;
288 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
289 bias-disable;
290 drive-push-pull;
291 slew-rate = <0>;
298 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
299 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
300 bias-disable;
304 /omit-if-no-ref/
305 ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
314 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
315 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
320 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
321 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
325 /omit-if-no-ref/
326 ethernet0_rgmii_pins_c: rgmii-2 {
335 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
336 bias-disable;
337 drive-push-pull;
338 slew-rate = <2>;
341 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
342 bias-disable;
343 drive-push-pull;
344 slew-rate = <0>;
350 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
351 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
352 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
353 bias-disable;
357 /omit-if-no-ref/
358 ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
367 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
368 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
372 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
373 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
374 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
378 /omit-if-no-ref/
379 ethernet0_rgmii_pins_d: rgmii-3 {
387 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
388 bias-disable;
389 drive-push-pull;
390 slew-rate = <2>;
393 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
394 bias-disable;
395 drive-push-pull;
396 slew-rate = <0>;
402 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
403 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
404 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
405 bias-disable;
409 /omit-if-no-ref/
410 ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 {
419 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
420 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
424 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
425 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
426 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
430 /omit-if-no-ref/
431 ethernet0_rgmii_pins_e: rgmii-4 {
439 bias-disable;
440 drive-push-pull;
441 slew-rate = <2>;
448 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
449 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
450 bias-disable;
454 /omit-if-no-ref/
455 ethernet0_rgmii_sleep_pins_e: rgmii-sleep-4 {
467 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
468 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
472 /omit-if-no-ref/
473 ethernet0_rmii_pins_a: rmii-0 {
478 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
479 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
480 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
481 bias-disable;
482 drive-push-pull;
483 slew-rate = <2>;
488 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
489 bias-disable;
493 /omit-if-no-ref/
494 ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
499 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
500 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
503 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
504 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
508 /omit-if-no-ref/
509 ethernet0_rmii_pins_b: rmii-1 {
512 <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
515 bias-disable;
516 drive-push-pull;
517 slew-rate = <1>;
520 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
521 bias-disable;
522 drive-push-pull;
523 slew-rate = <0>;
526 pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
529 bias-disable;
536 /omit-if-no-ref/
537 ethernet0_rmii_sleep_pins_b: rmii-sleep-1 {
539 pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
540 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */
543 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
551 /omit-if-no-ref/
552 ethernet0_rmii_pins_c: rmii-2 {
557 <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
558 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
559 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
560 bias-disable;
561 drive-push-pull;
562 slew-rate = <2>;
567 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
568 bias-disable;
572 /omit-if-no-ref/
573 ethernet0_rmii_sleep_pins_c: rmii-sleep-2 {
578 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
579 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
582 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
583 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
587 /omit-if-no-ref/
588 fmc_pins_a: fmc-0 {
590 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
591 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
592 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
593 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
594 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
595 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
596 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
597 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
600 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
602 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
603 bias-disable;
604 drive-push-pull;
605 slew-rate = <1>;
608 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
609 bias-pull-up;
613 /omit-if-no-ref/
614 fmc_sleep_pins_a: fmc-sleep-0 {
616 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
617 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
618 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
619 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
620 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
621 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
622 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
623 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
626 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
628 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
629 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
633 /omit-if-no-ref/
634 fmc_pins_b: fmc-1 {
636 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
637 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
639 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
640 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
641 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
642 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
645 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
652 <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
653 <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
654 <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
655 <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
657 bias-disable;
658 drive-push-pull;
659 slew-rate = <3>;
663 /omit-if-no-ref/
664 fmc_sleep_pins_b: fmc-sleep-1 {
666 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
667 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
669 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
670 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
671 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
672 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
675 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
682 <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
683 <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
684 <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
685 <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
690 /omit-if-no-ref/
691 i2c1_pins_a: i2c1-0 {
693 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
695 bias-disable;
696 drive-open-drain;
697 slew-rate = <0>;
701 /omit-if-no-ref/
702 i2c1_sleep_pins_a: i2c1-sleep-0 {
704 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
709 /omit-if-no-ref/
710 i2c1_pins_b: i2c1-1 {
714 bias-disable;
715 drive-open-drain;
716 slew-rate = <0>;
720 /omit-if-no-ref/
721 i2c1_sleep_pins_b: i2c1-sleep-1 {
728 /omit-if-no-ref/
729 i2c2_pins_a: i2c2-0 {
733 bias-disable;
734 drive-open-drain;
735 slew-rate = <0>;
739 /omit-if-no-ref/
740 i2c2_sleep_pins_a: i2c2-sleep-0 {
747 /omit-if-no-ref/
748 i2c2_pins_b1: i2c2-1 {
751 bias-disable;
752 drive-open-drain;
753 slew-rate = <0>;
757 /omit-if-no-ref/
758 i2c2_sleep_pins_b1: i2c2-sleep-1 {
764 /omit-if-no-ref/
765 i2c2_pins_c: i2c2-2 {
767 pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */
769 bias-disable;
770 drive-open-drain;
771 slew-rate = <0>;
775 /omit-if-no-ref/
776 i2c2_pins_sleep_c: i2c2-sleep-2 {
778 pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */
783 /omit-if-no-ref/
784 i2c5_pins_a: i2c5-0 {
786 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
787 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
788 bias-disable;
789 drive-open-drain;
790 slew-rate = <0>;
794 /omit-if-no-ref/
795 i2c5_sleep_pins_a: i2c5-sleep-0 {
797 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
798 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
803 /omit-if-no-ref/
804 i2c5_pins_b: i2c5-1 {
806 pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */
807 <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */
808 bias-disable;
809 drive-open-drain;
810 slew-rate = <0>;
814 /omit-if-no-ref/
815 i2c5_sleep_pins_b: i2c5-sleep-1 {
817 pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */
818 <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */
822 /omit-if-no-ref/
823 i2s2_pins_a: i2s2-0 {
826 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
827 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
828 slew-rate = <1>;
829 drive-push-pull;
830 bias-disable;
834 /omit-if-no-ref/
835 i2s2_sleep_pins_a: i2s2-sleep-0 {
838 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
839 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
843 /omit-if-no-ref/
844 i2s2_pins_b: i2s2-1 {
849 bias-disable;
850 drive-push-pull;
851 slew-rate = <1>;
855 /omit-if-no-ref/
856 i2s2_sleep_pins_b: i2s2-sleep-1 {
864 /omit-if-no-ref/
865 ltdc_pins_a: ltdc-0 {
869 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
874 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
885 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
887 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
890 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
892 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
894 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
895 bias-disable;
896 drive-push-pull;
897 slew-rate = <1>;
901 /omit-if-no-ref/
902 ltdc_sleep_pins_a: ltdc-sleep-0 {
906 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
911 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
922 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
924 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
927 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
929 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
931 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
935 /omit-if-no-ref/
936 ltdc_pins_b: ltdc-1 {
944 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
952 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
956 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
966 bias-disable;
967 drive-push-pull;
968 slew-rate = <1>;
972 /omit-if-no-ref/
973 ltdc_sleep_pins_b: ltdc-sleep-1 {
981 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
989 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
993 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
1006 /omit-if-no-ref/
1007 ltdc_pins_c: ltdc-2 {
1009 pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */
1010 <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */
1012 <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */
1013 <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */
1014 <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */
1021 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
1025 <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
1028 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
1030 bias-disable;
1031 drive-push-pull;
1032 slew-rate = <0>;
1036 bias-disable;
1037 drive-push-pull;
1038 slew-rate = <1>;
1042 /omit-if-no-ref/
1043 ltdc_sleep_pins_c: ltdc-sleep-2 {
1045 pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */
1046 <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */
1048 <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */
1049 <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */
1050 <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */
1057 <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */
1061 <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */
1064 <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */
1070 /omit-if-no-ref/
1071 ltdc_pins_d: ltdc-3 {
1074 bias-disable;
1075 drive-push-pull;
1076 slew-rate = <3>;
1080 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
1085 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
1086 <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */
1098 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
1101 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
1103 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
1106 bias-disable;
1107 drive-push-pull;
1108 slew-rate = <2>;
1112 /omit-if-no-ref/
1113 ltdc_sleep_pins_d: ltdc-sleep-3 {
1117 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
1122 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
1123 <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */
1135 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
1138 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
1140 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
1146 /omit-if-no-ref/
1147 ltdc_pins_e: ltdc-4 {
1152 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
1163 <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
1165 <STM32_PINMUX('D', 9, AF14)>, /* LTDC_B0 */
1168 <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */
1170 <STM32_PINMUX('A', 3, AF14)>, /* LTDC_B5 */
1172 <STM32_PINMUX('D', 8, AF14)>, /* LTDC_B7 */
1174 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
1176 bias-disable;
1177 drive-push-pull;
1178 slew-rate = <0>;
1183 bias-disable;
1184 drive-push-pull;
1185 slew-rate = <1>;
1189 /omit-if-no-ref/
1190 ltdc_sleep_pins_e: ltdc-sleep-4 {
1195 <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */
1200 <STM32_PINMUX('D', 9, ANALOG)>, /* LTDC_B0 */
1203 <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */
1205 <STM32_PINMUX('A', 3, ANALOG)>, /* LTDC_B5 */
1207 <STM32_PINMUX('D', 8, ANALOG)>, /* LTDC_B7 */
1214 <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */
1217 <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */
1223 /omit-if-no-ref/
1224 mco1_pins_a: mco1-0 {
1226 pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */
1227 bias-disable;
1228 drive-push-pull;
1229 slew-rate = <1>;
1233 /omit-if-no-ref/
1234 mco1_sleep_pins_a: mco1-sleep-0 {
1236 pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */
1240 /omit-if-no-ref/
1241 mco2_pins_a: mco2-0 {
1244 bias-disable;
1245 drive-push-pull;
1246 slew-rate = <2>;
1250 /omit-if-no-ref/
1251 mco2_sleep_pins_a: mco2-sleep-0 {
1257 /omit-if-no-ref/
1258 m_can1_pins_a: m-can1-0 {
1261 slew-rate = <1>;
1262 drive-push-pull;
1263 bias-disable;
1266 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
1267 bias-disable;
1271 /omit-if-no-ref/
1272 m_can1_sleep_pins_a: m_can1-sleep-0 {
1275 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
1279 /omit-if-no-ref/
1280 m_can1_pins_b: m-can1-1 {
1282 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
1283 slew-rate = <1>;
1284 drive-push-pull;
1285 bias-disable;
1288 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
1289 bias-disable;
1293 /omit-if-no-ref/
1294 m_can1_sleep_pins_b: m_can1-sleep-1 {
1296 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
1297 <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
1301 /omit-if-no-ref/
1302 m_can1_pins_c: m-can1-2 {
1305 slew-rate = <1>;
1306 drive-push-pull;
1307 bias-disable;
1311 bias-disable;
1315 /omit-if-no-ref/
1316 m_can1_sleep_pins_c: m_can1-sleep-2 {
1323 /omit-if-no-ref/
1324 m_can1_pins_d: m-can1-3 {
1326 pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
1327 slew-rate = <1>;
1328 drive-push-pull;
1329 bias-disable;
1332 pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
1333 bias-disable;
1337 /omit-if-no-ref/
1338 m_can1_sleep_pins_d: m_can1-sleep-3 {
1340 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* CAN1_TX */
1341 <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */
1345 /omit-if-no-ref/
1346 m_can2_pins_a: m-can2-0 {
1349 slew-rate = <1>;
1350 drive-push-pull;
1351 bias-disable;
1355 bias-disable;
1359 /omit-if-no-ref/
1360 m_can2_sleep_pins_a: m_can2-sleep-0 {
1367 /omit-if-no-ref/
1368 pwm1_pins_a: pwm1-0 {
1370 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
1373 bias-pull-down;
1374 drive-push-pull;
1375 slew-rate = <0>;
1379 /omit-if-no-ref/
1380 pwm1_sleep_pins_a: pwm1-sleep-0 {
1382 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
1388 /omit-if-no-ref/
1389 pwm1_pins_b: pwm1-1 {
1391 pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */
1392 bias-pull-down;
1393 drive-push-pull;
1394 slew-rate = <0>;
1398 /omit-if-no-ref/
1399 pwm1_sleep_pins_b: pwm1-sleep-1 {
1401 pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */
1405 /omit-if-no-ref/
1406 pwm1_pins_c: pwm1-2 {
1409 drive-push-pull;
1410 slew-rate = <0>;
1414 /omit-if-no-ref/
1415 pwm1_sleep_pins_c: pwm1-sleep-2 {
1421 /omit-if-no-ref/
1422 pwm2_pins_a: pwm2-0 {
1424 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
1425 bias-pull-down;
1426 drive-push-pull;
1427 slew-rate = <0>;
1431 /omit-if-no-ref/
1432 pwm2_sleep_pins_a: pwm2-sleep-0 {
1434 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
1438 /omit-if-no-ref/
1439 pwm3_pins_a: pwm3-0 {
1442 bias-pull-down;
1443 drive-push-pull;
1444 slew-rate = <0>;
1448 /omit-if-no-ref/
1449 pwm3_sleep_pins_a: pwm3-sleep-0 {
1455 /omit-if-no-ref/
1456 pwm3_pins_b: pwm3-1 {
1459 bias-disable;
1460 drive-push-pull;
1461 slew-rate = <0>;
1465 /omit-if-no-ref/
1466 pwm3_sleep_pins_b: pwm3-sleep-1 {
1472 /omit-if-no-ref/
1473 pwm4_pins_a: pwm4-0 {
1475 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
1476 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
1477 bias-pull-down;
1478 drive-push-pull;
1479 slew-rate = <0>;
1483 /omit-if-no-ref/
1484 pwm4_sleep_pins_a: pwm4-sleep-0 {
1486 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
1487 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
1491 /omit-if-no-ref/
1492 pwm4_pins_b: pwm4-1 {
1494 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
1495 bias-pull-down;
1496 drive-push-pull;
1497 slew-rate = <0>;
1501 /omit-if-no-ref/
1502 pwm4_sleep_pins_b: pwm4-sleep-1 {
1504 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
1508 /omit-if-no-ref/
1509 pwm5_pins_a: pwm5-0 {
1512 bias-pull-down;
1513 drive-push-pull;
1514 slew-rate = <0>;
1518 /omit-if-no-ref/
1519 pwm5_sleep_pins_a: pwm5-sleep-0 {
1525 /omit-if-no-ref/
1526 pwm5_pins_b: pwm5-1 {
1531 bias-disable;
1532 drive-push-pull;
1533 slew-rate = <0>;
1537 /omit-if-no-ref/
1538 pwm5_sleep_pins_b: pwm5-sleep-1 {
1546 /omit-if-no-ref/
1547 pwm8_pins_a: pwm8-0 {
1550 bias-pull-down;
1551 drive-push-pull;
1552 slew-rate = <0>;
1556 /omit-if-no-ref/
1557 pwm8_sleep_pins_a: pwm8-sleep-0 {
1563 /omit-if-no-ref/
1564 pwm8_pins_b: pwm8-1 {
1569 <STM32_PINMUX('C', 9, AF3)>; /* TIM8_CH4 */
1570 drive-push-pull;
1571 slew-rate = <0>;
1575 /omit-if-no-ref/
1576 pwm8_sleep_pins_b: pwm8-sleep-1 {
1581 <STM32_PINMUX('C', 9, ANALOG)>; /* TIM8_CH4 */
1585 /omit-if-no-ref/
1586 pwm12_pins_a: pwm12-0 {
1589 bias-pull-down;
1590 drive-push-pull;
1591 slew-rate = <0>;
1595 /omit-if-no-ref/
1596 pwm12_sleep_pins_a: pwm12-sleep-0 {
1602 /omit-if-no-ref/
1603 qspi_clk_pins_a: qspi-clk-0 {
1606 bias-disable;
1607 drive-push-pull;
1608 slew-rate = <3>;
1612 /omit-if-no-ref/
1613 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
1619 /omit-if-no-ref/
1620 qspi_bk1_pins_a: qspi-bk1-0 {
1623 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
1626 bias-disable;
1627 drive-push-pull;
1628 slew-rate = <1>;
1632 /omit-if-no-ref/
1633 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
1636 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
1642 /omit-if-no-ref/
1643 qspi_bk2_pins_a: qspi-bk2-0 {
1649 bias-disable;
1650 drive-push-pull;
1651 slew-rate = <1>;
1655 /omit-if-no-ref/
1656 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
1665 /omit-if-no-ref/
1666 qspi_cs1_pins_a: qspi-cs1-0 {
1669 bias-pull-up;
1670 drive-push-pull;
1671 slew-rate = <1>;
1675 /omit-if-no-ref/
1676 qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
1682 /omit-if-no-ref/
1683 qspi_cs2_pins_a: qspi-cs2-0 {
1686 bias-pull-up;
1687 drive-push-pull;
1688 slew-rate = <1>;
1692 /omit-if-no-ref/
1693 qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 {
1699 /omit-if-no-ref/
1700 rtc_rsvd_pins_a: rtc-rsvd-0 {
1706 /omit-if-no-ref/
1707 sai2a_pins_a: sai2a-0 {
1713 slew-rate = <0>;
1714 drive-push-pull;
1715 bias-disable;
1719 /omit-if-no-ref/
1720 sai2a_sleep_pins_a: sai2a-sleep-0 {
1729 /omit-if-no-ref/
1730 sai2a_pins_b: sai2a-1 {
1734 <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */
1735 slew-rate = <0>;
1736 drive-push-pull;
1737 bias-disable;
1741 /omit-if-no-ref/
1742 sai2a_sleep_pins_b: sai2a-sleep-1 {
1746 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */
1750 /omit-if-no-ref/
1751 sai2a_pins_c: sai2a-2 {
1753 pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */
1754 <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */
1755 <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */
1756 slew-rate = <0>;
1757 drive-push-pull;
1758 bias-disable;
1762 /omit-if-no-ref/
1763 sai2a_sleep_pins_c: sai2a-sleep-2 {
1765 pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */
1766 <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */
1767 <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */
1771 /omit-if-no-ref/
1772 sai2b_pins_a: sai2b-0 {
1777 slew-rate = <0>;
1778 drive-push-pull;
1779 bias-disable;
1783 bias-disable;
1787 /omit-if-no-ref/
1788 sai2b_sleep_pins_a: sai2b-sleep-0 {
1797 /omit-if-no-ref/
1798 sai2b_pins_b: sai2b-1 {
1801 bias-disable;
1805 /omit-if-no-ref/
1806 sai2b_sleep_pins_b: sai2b-sleep-1 {
1812 /omit-if-no-ref/
1813 sai2b_pins_c: sai2b-2 {
1816 bias-disable;
1820 /omit-if-no-ref/
1821 sai2b_sleep_pins_c: sai2b-sleep-2 {
1827 /omit-if-no-ref/
1828 sai2b_pins_d: sai2b-3 {
1833 slew-rate = <0>;
1834 drive-push-pull;
1835 bias-disable;
1839 bias-disable;
1843 /omit-if-no-ref/
1844 sai2b_sleep_pins_d: sai2b-sleep-3 {
1853 /omit-if-no-ref/
1854 sai4a_pins_a: sai4a-0 {
1857 slew-rate = <0>;
1858 drive-push-pull;
1859 bias-disable;
1863 /omit-if-no-ref/
1864 sai4a_sleep_pins_a: sai4a-sleep-0 {
1870 /omit-if-no-ref/
1871 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
1874 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1877 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1878 slew-rate = <1>;
1879 drive-push-pull;
1880 bias-disable;
1884 slew-rate = <2>;
1885 drive-push-pull;
1886 bias-disable;
1890 /omit-if-no-ref/
1891 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
1894 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1897 slew-rate = <1>;
1898 drive-push-pull;
1899 bias-disable;
1903 slew-rate = <2>;
1904 drive-push-pull;
1905 bias-disable;
1908 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1909 slew-rate = <1>;
1910 drive-open-drain;
1911 bias-disable;
1915 /omit-if-no-ref/
1916 sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
1919 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1922 slew-rate = <1>;
1923 drive-push-pull;
1924 bias-disable;
1928 /omit-if-no-ref/
1929 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
1932 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
1936 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
1940 /omit-if-no-ref/
1941 sdmmc1_b4_pins_b: sdmmc1-b4-1 {
1944 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1947 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1948 slew-rate = <1>;
1949 drive-push-pull;
1950 bias-disable;
1954 slew-rate = <2>;
1955 drive-push-pull;
1956 bias-disable;
1960 /omit-if-no-ref/
1961 sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 {
1964 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1967 slew-rate = <1>;
1968 drive-push-pull;
1969 bias-disable;
1973 slew-rate = <2>;
1974 drive-push-pull;
1975 bias-disable;
1978 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1979 slew-rate = <1>;
1980 drive-open-drain;
1981 bias-disable;
1985 /omit-if-no-ref/
1986 sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 {
1989 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
1993 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
1997 /omit-if-no-ref/
1998 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
2002 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
2003 slew-rate = <1>;
2004 drive-push-pull;
2005 bias-pull-up;
2009 bias-pull-up;
2013 /omit-if-no-ref/
2014 sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 {
2018 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
2019 slew-rate = <1>;
2020 drive-push-pull;
2021 bias-pull-up;
2025 /omit-if-no-ref/
2026 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
2030 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
2035 /omit-if-no-ref/
2036 sdmmc1_dir_pins_b: sdmmc1-dir-1 {
2040 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
2041 slew-rate = <1>;
2042 drive-push-pull;
2043 bias-pull-up;
2047 bias-pull-up;
2051 /omit-if-no-ref/
2052 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
2056 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
2061 /omit-if-no-ref/
2062 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
2069 slew-rate = <1>;
2070 drive-push-pull;
2071 bias-pull-up;
2075 slew-rate = <2>;
2076 drive-push-pull;
2077 bias-pull-up;
2081 /omit-if-no-ref/
2082 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
2088 slew-rate = <1>;
2089 drive-push-pull;
2090 bias-pull-up;
2094 slew-rate = <2>;
2095 drive-push-pull;
2096 bias-pull-up;
2100 slew-rate = <1>;
2101 drive-open-drain;
2102 bias-pull-up;
2106 /omit-if-no-ref/
2107 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
2118 /omit-if-no-ref/
2119 sdmmc2_b4_pins_b: sdmmc2-b4-1 {
2126 slew-rate = <1>;
2127 drive-push-pull;
2128 bias-disable;
2132 slew-rate = <2>;
2133 drive-push-pull;
2134 bias-disable;
2138 /omit-if-no-ref/
2139 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
2145 slew-rate = <1>;
2146 drive-push-pull;
2147 bias-disable;
2151 slew-rate = <2>;
2152 drive-push-pull;
2153 bias-disable;
2157 slew-rate = <1>;
2158 drive-open-drain;
2159 bias-disable;
2163 /omit-if-no-ref/
2164 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
2166 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
2167 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
2169 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
2170 slew-rate = <1>;
2171 drive-push-pull;
2172 bias-pull-up;
2176 /omit-if-no-ref/
2177 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
2179 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
2180 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
2182 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
2186 /omit-if-no-ref/
2187 sdmmc2_d47_pins_b: sdmmc2-d47-1 {
2189 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
2190 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
2193 slew-rate = <1>;
2194 drive-push-pull;
2195 bias-disable;
2199 /omit-if-no-ref/
2200 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
2202 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
2203 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
2209 /omit-if-no-ref/
2210 sdmmc2_d47_pins_c: sdmmc2-d47-2 {
2212 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
2213 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
2216 slew-rate = <1>;
2217 drive-push-pull;
2218 bias-pull-up;
2222 /omit-if-no-ref/
2223 sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 {
2225 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
2226 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
2232 /omit-if-no-ref/
2233 sdmmc2_d47_pins_d: sdmmc2-d47-3 {
2235 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
2236 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
2239 slew-rate = <1>;
2240 drive-push-pull;
2241 bias-pull-up;
2245 /omit-if-no-ref/
2246 sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
2248 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
2249 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
2255 /omit-if-no-ref/
2256 sdmmc2_d47_pins_e: sdmmc2-d47-4 {
2258 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
2259 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
2261 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
2262 slew-rate = <1>;
2263 drive-push-pull;
2264 bias-pull-up;
2268 /omit-if-no-ref/
2269 sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 {
2271 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
2272 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
2274 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
2278 /omit-if-no-ref/
2279 sdmmc3_b4_pins_a: sdmmc3-b4-0 {
2284 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
2285 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
2286 slew-rate = <1>;
2287 drive-push-pull;
2288 bias-pull-up;
2292 slew-rate = <2>;
2293 drive-push-pull;
2294 bias-pull-up;
2298 /omit-if-no-ref/
2299 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
2304 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
2305 slew-rate = <1>;
2306 drive-push-pull;
2307 bias-pull-up;
2311 slew-rate = <2>;
2312 drive-push-pull;
2313 bias-pull-up;
2316 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
2317 slew-rate = <1>;
2318 drive-open-drain;
2319 bias-pull-up;
2323 /omit-if-no-ref/
2324 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
2329 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
2331 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
2335 /omit-if-no-ref/
2336 sdmmc3_b4_pins_b: sdmmc3-b4-1 {
2340 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
2341 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
2342 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
2343 slew-rate = <1>;
2344 drive-push-pull;
2345 bias-pull-up;
2349 slew-rate = <2>;
2350 drive-push-pull;
2351 bias-pull-up;
2355 /omit-if-no-ref/
2356 sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 {
2360 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
2361 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
2362 slew-rate = <1>;
2363 drive-push-pull;
2364 bias-pull-up;
2368 slew-rate = <2>;
2369 drive-push-pull;
2370 bias-pull-up;
2373 pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */
2374 slew-rate = <1>;
2375 drive-open-drain;
2376 bias-pull-up;
2380 /omit-if-no-ref/
2381 sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 {
2385 <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
2386 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
2388 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
2392 /omit-if-no-ref/
2393 spdifrx_pins_a: spdifrx-0 {
2396 bias-disable;
2400 /omit-if-no-ref/
2401 spdifrx_sleep_pins_a: spdifrx-sleep-0 {
2407 /omit-if-no-ref/
2408 spi1_pins_b: spi1-1 {
2410 pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
2412 bias-disable;
2413 drive-push-pull;
2414 slew-rate = <1>;
2418 pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
2419 bias-disable;
2423 /omit-if-no-ref/
2424 spi2_pins_a: spi2-0 {
2428 bias-disable;
2429 drive-push-pull;
2430 slew-rate = <1>;
2435 bias-disable;
2439 /omit-if-no-ref/
2440 spi2_pins_b: spi2-1 {
2442 pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
2444 bias-disable;
2445 drive-push-pull;
2446 slew-rate = <1>;
2451 bias-disable;
2455 /omit-if-no-ref/
2456 spi2_pins_c: spi2-2 {
2458 pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
2460 bias-disable;
2461 drive-push-pull;
2466 bias-pull-down;
2470 /omit-if-no-ref/
2471 spi4_pins_a: spi4-0 {
2475 bias-disable;
2476 drive-push-pull;
2477 slew-rate = <1>;
2481 bias-disable;
2485 /omit-if-no-ref/
2486 spi5_pins_a: spi5-0 {
2489 <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
2490 bias-disable;
2491 drive-push-pull;
2492 slew-rate = <1>;
2497 bias-disable;
2501 /omit-if-no-ref/
2502 stusb1600_pins_a: stusb1600-0 {
2505 bias-pull-up;
2509 /omit-if-no-ref/
2510 uart4_pins_a: uart4-0 {
2513 bias-disable;
2514 drive-push-pull;
2515 slew-rate = <0>;
2519 bias-disable;
2523 /omit-if-no-ref/
2524 uart4_idle_pins_a: uart4-idle-0 {
2530 bias-disable;
2534 /omit-if-no-ref/
2535 uart4_sleep_pins_a: uart4-sleep-0 {
2542 /omit-if-no-ref/
2543 uart4_pins_b: uart4-1 {
2545 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
2546 bias-disable;
2547 drive-push-pull;
2548 slew-rate = <0>;
2552 bias-disable;
2556 /omit-if-no-ref/
2557 uart4_pins_c: uart4-2 {
2560 bias-disable;
2561 drive-push-pull;
2562 slew-rate = <0>;
2566 bias-disable;
2570 /omit-if-no-ref/
2571 uart4_pins_d: uart4-3 {
2573 pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */
2574 bias-disable;
2575 drive-push-pull;
2576 slew-rate = <0>;
2580 bias-disable;
2584 /omit-if-no-ref/
2585 uart4_idle_pins_d: uart4-idle-3 {
2587 pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */
2591 bias-disable;
2595 /omit-if-no-ref/
2596 uart4_sleep_pins_d: uart4-sleep-3 {
2598 pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */
2603 /omit-if-no-ref/
2604 uart5_pins_a: uart5-0 {
2607 bias-disable;
2608 drive-push-pull;
2609 slew-rate = <0>;
2613 bias-disable;
2617 /omit-if-no-ref/
2618 uart7_pins_a: uart7-0 {
2621 bias-disable;
2622 drive-push-pull;
2623 slew-rate = <0>;
2628 <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
2629 bias-disable;
2633 /omit-if-no-ref/
2634 uart7_pins_b: uart7-1 {
2637 bias-disable;
2638 drive-push-pull;
2639 slew-rate = <0>;
2643 bias-disable;
2647 /omit-if-no-ref/
2648 uart7_pins_c: uart7-2 {
2651 bias-disable;
2652 drive-push-pull;
2653 slew-rate = <0>;
2657 bias-pull-up;
2661 /omit-if-no-ref/
2662 uart7_idle_pins_c: uart7-idle-2 {
2668 bias-pull-up;
2672 /omit-if-no-ref/
2673 uart7_sleep_pins_c: uart7-sleep-2 {
2680 /omit-if-no-ref/
2681 uart8_pins_a: uart8-0 {
2683 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
2684 bias-disable;
2685 drive-push-pull;
2686 slew-rate = <0>;
2690 bias-disable;
2694 /omit-if-no-ref/
2695 uart8_rtscts_pins_a: uart8rtscts-0 {
2699 bias-disable;
2703 /omit-if-no-ref/
2704 usart1_pins_a: usart1-0 {
2706 pinmux = <STM32_PINMUX('A', 12, AF7)>; /* USART1_RTS */
2707 bias-disable;
2708 drive-push-pull;
2709 slew-rate = <0>;
2712 pinmux = <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
2713 bias-disable;
2717 /omit-if-no-ref/
2718 usart1_idle_pins_a: usart1-idle-0 {
2720 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
2721 <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
2725 /omit-if-no-ref/
2726 usart1_sleep_pins_a: usart1-sleep-0 {
2728 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
2729 <STM32_PINMUX('A', 11, ANALOG)>; /* USART1_CTS_NSS */
2733 /omit-if-no-ref/
2734 usart2_pins_a: usart2-0 {
2737 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
2738 bias-disable;
2739 drive-push-pull;
2740 slew-rate = <0>;
2743 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
2744 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
2745 bias-disable;
2749 /omit-if-no-ref/
2750 usart2_sleep_pins_a: usart2-sleep-0 {
2753 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
2754 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
2755 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
2759 /omit-if-no-ref/
2760 usart2_pins_b: usart2-1 {
2763 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
2764 bias-disable;
2765 drive-push-pull;
2766 slew-rate = <0>;
2771 bias-disable;
2775 /omit-if-no-ref/
2776 usart2_sleep_pins_b: usart2-sleep-1 {
2779 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
2785 /omit-if-no-ref/
2786 usart2_pins_c: usart2-2 {
2788 pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
2789 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
2790 bias-disable;
2791 drive-push-pull;
2792 slew-rate = <0>;
2795 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
2796 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
2797 bias-disable;
2801 /omit-if-no-ref/
2802 usart2_idle_pins_c: usart2-idle-2 {
2804 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
2805 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
2808 pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
2809 bias-disable;
2810 drive-push-pull;
2811 slew-rate = <0>;
2814 pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
2815 bias-disable;
2819 /omit-if-no-ref/
2820 usart2_sleep_pins_c: usart2-sleep-2 {
2822 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
2823 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
2824 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
2825 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
2829 /omit-if-no-ref/
2830 usart3_pins_a: usart3-0 {
2833 bias-disable;
2834 drive-push-pull;
2835 slew-rate = <0>;
2839 bias-disable;
2843 /omit-if-no-ref/
2844 usart3_idle_pins_a: usart3-idle-0 {
2850 bias-disable;
2854 /omit-if-no-ref/
2855 usart3_sleep_pins_a: usart3-sleep-0 {
2862 /omit-if-no-ref/
2863 usart3_pins_b: usart3-1 {
2867 bias-disable;
2868 drive-push-pull;
2869 slew-rate = <0>;
2874 bias-pull-up;
2878 /omit-if-no-ref/
2879 usart3_idle_pins_b: usart3-idle-1 {
2886 bias-disable;
2887 drive-push-pull;
2888 slew-rate = <0>;
2892 bias-pull-up;
2896 /omit-if-no-ref/
2897 usart3_sleep_pins_b: usart3-sleep-1 {
2906 /omit-if-no-ref/
2907 usart3_pins_c: usart3-2 {
2911 bias-disable;
2912 drive-push-pull;
2913 slew-rate = <0>;
2918 bias-pull-up;
2922 /omit-if-no-ref/
2923 usart3_idle_pins_c: usart3-idle-2 {
2930 bias-disable;
2931 drive-push-pull;
2932 slew-rate = <0>;
2936 bias-pull-up;
2940 /omit-if-no-ref/
2941 usart3_sleep_pins_c: usart3-sleep-2 {
2950 /omit-if-no-ref/
2951 usart3_pins_d: usart3-3 {
2955 bias-disable;
2956 drive-push-pull;
2957 slew-rate = <0>;
2960 pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */
2961 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
2962 bias-disable;
2966 /omit-if-no-ref/
2967 usart3_idle_pins_d: usart3-idle-3 {
2971 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
2974 pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */
2975 bias-disable;
2979 /omit-if-no-ref/
2980 usart3_sleep_pins_d: usart3-sleep-3 {
2984 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
2985 <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */
2989 /omit-if-no-ref/
2990 usart3_pins_e: usart3-4 {
2994 bias-disable;
2995 drive-push-pull;
2996 slew-rate = <0>;
3000 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
3001 bias-pull-up;
3005 /omit-if-no-ref/
3006 usart3_idle_pins_e: usart3-idle-4 {
3009 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
3013 bias-disable;
3014 drive-push-pull;
3015 slew-rate = <0>;
3019 bias-pull-up;
3023 /omit-if-no-ref/
3024 usart3_sleep_pins_e: usart3-sleep-4 {
3028 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
3033 /omit-if-no-ref/
3034 usart3_pins_f: usart3-5 {
3037 <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS */
3038 bias-disable;
3039 drive-push-pull;
3040 slew-rate = <0>;
3044 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
3045 bias-disable;
3049 /omit-if-no-ref/
3050 usbotg_hs_pins_a: usbotg-hs-0 {
3052 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
3056 /omit-if-no-ref/
3057 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
3059 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
3060 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
3066 /omit-if-no-ref/
3067 i2c2_pins_b2: i2c2-0 {
3070 bias-disable;
3071 drive-open-drain;
3072 slew-rate = <0>;
3076 /omit-if-no-ref/
3077 i2c2_sleep_pins_b2: i2c2-sleep-0 {
3083 /omit-if-no-ref/
3084 i2c4_pins_a: i2c4-0 {
3088 bias-disable;
3089 drive-open-drain;
3090 slew-rate = <0>;
3094 /omit-if-no-ref/
3095 i2c4_sleep_pins_a: i2c4-sleep-0 {
3102 /omit-if-no-ref/
3103 i2c6_pins_a: i2c6-0 {
3107 bias-disable;
3108 drive-open-drain;
3109 slew-rate = <0>;
3113 /omit-if-no-ref/
3114 i2c6_sleep_pins_a: i2c6-sleep-0 {
3121 /omit-if-no-ref/
3122 spi1_pins_a: spi1-0 {
3126 bias-disable;
3127 drive-push-pull;
3128 slew-rate = <1>;
3132 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
3133 bias-disable;
3137 /omit-if-no-ref/
3138 spi1_sleep_pins_a: spi1-sleep-0 {
3141 <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
3146 /omit-if-no-ref/
3147 usart1_pins_b: usart1-1 {
3150 bias-disable;
3151 drive-push-pull;
3152 slew-rate = <0>;
3156 bias-disable;
3160 /omit-if-no-ref/
3161 usart1_idle_pins_b: usart1-idle-1 {
3167 bias-disable;
3171 /omit-if-no-ref/
3172 usart1_sleep_pins_b: usart1-sleep-1 {