Lines Matching full:rcc
117 clocks = <&rcc TIM2_K>;
152 clocks = <&rcc TIM3_K>;
188 clocks = <&rcc TIM4_K>;
222 clocks = <&rcc TIM5_K>;
258 clocks = <&rcc TIM6_K>;
283 clocks = <&rcc TIM7_K>;
307 clocks = <&rcc LPTIM1_K>;
350 clocks = <&rcc SPI2_K>;
351 resets = <&rcc SPI2_R>;
375 clocks = <&rcc SPI3_K>;
376 resets = <&rcc SPI3_R>;
389 clocks = <&rcc SPDIF_K>;
402 clocks = <&rcc USART3_K>;
403 resets = <&rcc USART3_R>;
415 clocks = <&rcc UART4_K>;
416 resets = <&rcc UART4_R>;
428 clocks = <&rcc UART5_K>;
429 resets = <&rcc UART5_R>;
443 clocks = <&rcc I2C1_K>;
444 resets = <&rcc I2C1_R>;
461 clocks = <&rcc I2C2_K>;
462 resets = <&rcc I2C2_R>;
477 clocks = <&rcc UART7_K>;
478 resets = <&rcc UART7_R>;
490 clocks = <&rcc UART8_K>;
491 resets = <&rcc UART8_R>;
509 clocks = <&rcc TIM1_K>;
550 clocks = <&rcc TIM8_K>;
585 clocks = <&rcc USART6_K>;
586 resets = <&rcc USART6_R>;
609 clocks = <&rcc SPI1_K>;
610 resets = <&rcc SPI1_R>;
626 resets = <&rcc SAI1_R>;
633 clocks = <&rcc SAI1_K>;
643 clocks = <&rcc SAI1_K>;
657 resets = <&rcc SAI2_R>;
664 clocks = <&rcc SAI2_K>;
674 clocks = <&rcc SAI2_K>;
684 clocks = <&rcc DFSDM_K>;
722 clocks = <&rcc DMA1>;
723 resets = <&rcc DMA1_R>;
740 clocks = <&rcc DMA2>;
741 resets = <&rcc DMA2_R>;
750 clocks = <&rcc DMAMUX1>;
751 resets = <&rcc DMAMUX1_R>;
758 rcc: rcc@50000000 { label
759 compatible = "st,stm32mp13-rcc", "syscon";
877 clocks = <&rcc SYSCFG>;
884 clocks = <&rcc LPTIM4_K>;
905 clocks = <&rcc LPTIM5_K>;
926 clocks = <&rcc MDMA>;
935 clocks = <&rcc CRC1>;
942 clocks = <&usbphyc>, <&rcc USBH>;
943 resets = <&rcc USBH_R>;
951 clocks = <&usbphyc>, <&rcc USBH>;
952 resets = <&rcc USBH_R>;
961 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
1012 clocks = <&rcc ADC2>, <&rcc ADC2_K>;
1055 clocks = <&rcc USBO_K>;
1057 resets = <&rcc USBO_R>;
1074 clocks = <&rcc USART1_K>;
1075 resets = <&rcc USART1_R>;
1088 clocks = <&rcc USART2_K>;
1089 resets = <&rcc USART2_R>;
1114 clocks = <&rcc SPI4_K>;
1115 resets = <&rcc SPI4_R>;
1129 clocks = <&rcc SPI5_K>;
1130 resets = <&rcc SPI5_R>;
1146 clocks = <&rcc I2C3_K>;
1147 resets = <&rcc I2C3_R>;
1165 clocks = <&rcc I2C4_K>;
1166 resets = <&rcc I2C4_R>;
1184 clocks = <&rcc I2C5_K>;
1185 resets = <&rcc I2C5_R>;
1204 clocks = <&rcc TIM12_K>;
1234 clocks = <&rcc TIM13_K>;
1264 clocks = <&rcc TIM14_K>;
1294 clocks = <&rcc TIM15_K>;
1329 clocks = <&rcc TIM16_K>;
1362 clocks = <&rcc TIM17_K>;
1394 clocks = <&rcc LPTIM2_K>;
1429 clocks = <&rcc LPTIM3_K>;
1457 clocks = <&rcc HASH1>;
1458 resets = <&rcc HASH1_R>;
1468 clocks = <&rcc RNG1_K>;
1469 resets = <&rcc RNG1_R>;
1484 clocks = <&rcc FMC_K>;
1485 resets = <&rcc FMC_R>;
1518 clocks = <&rcc QSPI_K>;
1519 resets = <&rcc QSPI_R>;
1529 clocks = <&rcc SDMMC1_K>;
1531 resets = <&rcc SDMMC1_R>;
1544 clocks = <&rcc SDMMC2_K>;
1546 resets = <&rcc SDMMC2_R>;
1566 clocks = <&rcc ETH1MAC>,
1567 <&rcc ETH1TX>,
1568 <&rcc ETH1RX>,
1569 <&rcc ETH1STP>,
1570 <&rcc ETH1CK_K>;
1592 clocks = <&rcc USBPHY_K>;
1593 resets = <&rcc USBPHY_R>;
1629 clocks = <&rcc GPIOA>;
1641 clocks = <&rcc GPIOB>;
1653 clocks = <&rcc GPIOC>;
1665 clocks = <&rcc GPIOD>;
1677 clocks = <&rcc GPIOE>;
1689 clocks = <&rcc GPIOF>;
1701 clocks = <&rcc GPIOG>;
1713 clocks = <&rcc GPIOH>;
1725 clocks = <&rcc GPIOI>;