Lines Matching +full:6 +full:e +full:- +full:7
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 /omit-if-no-ref/
10 adc1_pins_a: adc1-pins-0 {
16 /omit-if-no-ref/
17 adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
24 /omit-if-no-ref/
25 adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
32 /omit-if-no-ref/
33 dcmipp_pins_a: dcmi-0 {
37 <STM32_PINMUX('B', 7, AF14)>,/* DCMI_PIXCLK */
41 <STM32_PINMUX('E', 4, AF13)>,/* DCMI_D3 */
45 <STM32_PINMUX('E', 14, AF13)>;/* DCMI_D7 */
46 bias-disable;
50 /omit-if-no-ref/
51 dcmipp_sleep_pins_a: dcmi-sleep-0 {
55 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_PIXCLK */
59 <STM32_PINMUX('E', 4, ANALOG)>,/* DCMI_D3 */
63 <STM32_PINMUX('E', 14, ANALOG)>;/* DCMI_D7 */
67 /omit-if-no-ref/
68 eth1_rgmii_pins_a: eth1-rgmii-0 {
73 <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */
78 bias-disable;
79 drive-push-pull;
80 slew-rate = <2>;
88 <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
89 <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
90 bias-disable;
94 /omit-if-no-ref/
95 eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
99 bias-disable;
100 drive-push-pull;
101 slew-rate = <2>;
108 <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */
115 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */
116 <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */
120 /omit-if-no-ref/
121 eth1_rmii_pins_a: eth1-rmii-0 {
129 bias-disable;
130 drive-push-pull;
131 slew-rate = <1>;
138 bias-disable;
142 /omit-if-no-ref/
143 eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 {
157 /omit-if-no-ref/
158 eth2_rgmii_pins_a: eth2-rgmii-0 {
160 pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */
163 <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */
164 <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */
166 <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */
168 bias-disable;
169 drive-push-pull;
170 slew-rate = <2>;
175 <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */
176 <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */
180 bias-disable;
184 /omit-if-no-ref/
185 eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
187 pinmux = <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */
189 bias-disable;
190 drive-push-pull;
191 slew-rate = <2>;
195 pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
198 <STM32_PINMUX('E', 6, ANALOG)>, /* ETH_RGMII_TXD3 */
199 <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_TX_CTL */
202 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
203 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
210 /omit-if-no-ref/
211 eth2_rmii_pins_a: eth2-rmii-0 {
213 pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */
216 <STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */
219 bias-disable;
220 drive-push-pull;
221 slew-rate = <1>;
226 <STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */
228 bias-disable;
232 /omit-if-no-ref/
233 eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 {
235 pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */
238 <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */
242 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */
247 /omit-if-no-ref/
248 goodix_pins_a: goodix-0 {
251 * via the pinctrl not the driver (a pull-down resistor
257 output-high;
258 bias-pull-up;
261 * Interrupt line must have a pull-down resistor
266 bias-pull-down;
270 /omit-if-no-ref/
271 i2c1_pins_a: i2c1-0 {
274 <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
275 bias-disable;
276 drive-open-drain;
277 slew-rate = <0>;
281 /omit-if-no-ref/
282 i2c1_sleep_pins_a: i2c1-sleep-0 {
285 <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
289 /omit-if-no-ref/
290 i2c5_pins_a: i2c5-0 {
293 <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
294 bias-disable;
295 drive-open-drain;
296 slew-rate = <0>;
300 /omit-if-no-ref/
301 i2c5_sleep_pins_a: i2c5-sleep-0 {
304 <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
308 /omit-if-no-ref/
309 i2c5_pins_b: i2c5-1 {
312 <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */
313 bias-disable;
314 drive-open-drain;
315 slew-rate = <0>;
319 /omit-if-no-ref/
320 i2c5_sleep_pins_b: i2c5-sleep-1 {
323 <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */
327 /omit-if-no-ref/
328 ltdc_pins_a: ltdc-0 {
331 <STM32_PINMUX('C', 6, AF14)>, /* LCD_HSYNC */
334 <STM32_PINMUX('G', 7, AF14)>, /* LCD_R2 */
337 <STM32_PINMUX('E', 7, AF14)>, /* LCD_R5 */
338 <STM32_PINMUX('E', 13, AF14)>, /* LCD_R6 */
339 <STM32_PINMUX('E', 9, AF14)>, /* LCD_R7 */
344 <STM32_PINMUX('C', 7, AF14)>, /* LCD_G6 */
349 <STM32_PINMUX('E', 0, AF14)>, /* LCD_B5 */
350 <STM32_PINMUX('B', 6, AF7)>, /* LCD_B6 */
352 bias-disable;
353 drive-push-pull;
354 slew-rate = <0>;
358 /omit-if-no-ref/
359 ltdc_sleep_pins_a: ltdc-sleep-0 {
362 <STM32_PINMUX('C', 6, ANALOG)>, /* LCD_HSYNC */
365 <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R2 */
368 <STM32_PINMUX('E', 7, ANALOG)>, /* LCD_R5 */
369 <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_R6 */
370 <STM32_PINMUX('E', 9, ANALOG)>, /* LCD_R7 */
375 <STM32_PINMUX('C', 7, ANALOG)>, /* LCD_G6 */
380 <STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B5 */
381 <STM32_PINMUX('B', 6, ANALOG)>, /* LCD_B6 */
386 /omit-if-no-ref/
387 m_can1_pins_a: m-can1-0 {
390 slew-rate = <1>;
391 drive-push-pull;
392 bias-disable;
396 bias-disable;
400 /omit-if-no-ref/
401 m_can1_sleep_pins_a: m_can1-sleep-0 {
408 /omit-if-no-ref/
409 m_can2_pins_a: m-can2-0 {
412 slew-rate = <1>;
413 drive-push-pull;
414 bias-disable;
417 pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */
418 bias-disable;
422 /omit-if-no-ref/
423 m_can2_sleep_pins_a: m_can2-sleep-0 {
426 <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */
430 /omit-if-no-ref/
431 mcp23017_pins_a: mcp23017-0 {
434 bias-pull-up;
438 /omit-if-no-ref/
439 pwm3_pins_a: pwm3-0 {
442 bias-pull-down;
443 drive-push-pull;
444 slew-rate = <0>;
448 /omit-if-no-ref/
449 pwm3_sleep_pins_a: pwm3-sleep-0 {
455 /omit-if-no-ref/
456 pwm4_pins_a: pwm4-0 {
459 bias-pull-down;
460 drive-push-pull;
461 slew-rate = <0>;
465 /omit-if-no-ref/
466 pwm4_sleep_pins_a: pwm4-sleep-0 {
472 /omit-if-no-ref/
473 pwm5_pins_a: pwm5-0 {
476 bias-pull-down;
477 drive-push-pull;
478 slew-rate = <0>;
482 /omit-if-no-ref/
483 pwm5_sleep_pins_a: pwm5-sleep-0 {
489 /omit-if-no-ref/
490 pwm8_pins_a: pwm8-0 {
492 pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
493 bias-pull-down;
494 drive-push-pull;
495 slew-rate = <0>;
499 /omit-if-no-ref/
500 pwm8_sleep_pins_a: pwm8-sleep-0 {
502 pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
506 /omit-if-no-ref/
507 pwm13_pins_a: pwm13-0 {
509 pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */
510 bias-pull-down;
511 drive-push-pull;
512 slew-rate = <0>;
516 /omit-if-no-ref/
517 pwm13_sleep_pins_a: pwm13-sleep-0 {
519 pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */
523 /omit-if-no-ref/
524 pwm14_pins_a: pwm14-0 {
527 bias-pull-down;
528 drive-push-pull;
529 slew-rate = <0>;
533 /omit-if-no-ref/
534 pwm14_sleep_pins_a: pwm14-sleep-0 {
540 /omit-if-no-ref/
541 qspi_clk_pins_a: qspi-clk-0 {
544 bias-disable;
545 drive-push-pull;
546 slew-rate = <3>;
550 /omit-if-no-ref/
551 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
557 /omit-if-no-ref/
558 qspi_bk1_pins_a: qspi-bk1-0 {
563 <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */
564 bias-disable;
565 drive-push-pull;
566 slew-rate = <1>;
570 /omit-if-no-ref/
571 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
576 <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */
580 /omit-if-no-ref/
581 qspi_cs1_pins_a: qspi-cs1-0 {
584 bias-pull-up;
585 drive-push-pull;
586 slew-rate = <1>;
590 /omit-if-no-ref/
591 qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
597 /omit-if-no-ref/
598 rtc_rsvd_pins_a: rtc-rsvd-0 {
604 /omit-if-no-ref/
605 sai1a_pins_a: sai1a-0 {
608 <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */
609 <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */
610 slew-rate = <0>;
611 drive-push-pull;
612 bias-disable;
616 /omit-if-no-ref/
617 sai1a_sleep_pins_a: sai1a-sleep-0 {
620 <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */
621 <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */
625 /omit-if-no-ref/
626 sai1b_pins_a: sai1b-0 {
629 bias-disable;
633 /omit-if-no-ref/
634 sai1b_sleep_pins_a: sai1b-sleep-0 {
640 /omit-if-no-ref/
641 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
648 slew-rate = <1>;
649 drive-push-pull;
650 bias-disable;
654 /omit-if-no-ref/
655 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
661 slew-rate = <1>;
662 drive-push-pull;
663 bias-disable;
667 slew-rate = <1>;
668 drive-open-drain;
669 bias-disable;
673 /omit-if-no-ref/
674 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
685 /omit-if-no-ref/
686 sdmmc1_clk_pins_a: sdmmc1-clk-0 {
689 slew-rate = <1>;
690 drive-push-pull;
691 bias-disable;
695 /omit-if-no-ref/
696 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
702 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
703 slew-rate = <1>;
704 drive-push-pull;
705 bias-pull-up;
709 /omit-if-no-ref/
710 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
716 slew-rate = <1>;
717 drive-push-pull;
718 bias-pull-up;
721 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
722 slew-rate = <1>;
723 drive-open-drain;
724 bias-pull-up;
728 /omit-if-no-ref/
729 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
735 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
736 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
740 /omit-if-no-ref/
741 sdmmc2_clk_pins_a: sdmmc2-clk-0 {
743 pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
744 slew-rate = <1>;
745 drive-push-pull;
746 bias-pull-up;
750 /omit-if-no-ref/
751 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
755 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
756 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
757 slew-rate = <1>;
758 drive-push-pull;
759 bias-pull-up;
763 /omit-if-no-ref/
764 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
768 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
769 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
773 /omit-if-no-ref/
774 spi2_pins_a: spi2-0 {
778 bias-disable;
779 drive-push-pull;
780 slew-rate = <1>;
785 bias-disable;
789 /omit-if-no-ref/
790 spi2_sleep_pins_a: spi2-sleep-0 {
798 /omit-if-no-ref/
799 spi3_pins_a: spi3-0 {
803 bias-disable;
804 drive-push-pull;
805 slew-rate = <1>;
810 bias-disable;
814 /omit-if-no-ref/
815 spi3_sleep_pins_a: spi3-sleep-0 {
823 /omit-if-no-ref/
824 spi5_pins_a: spi5-0 {
826 pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
828 bias-disable;
829 drive-push-pull;
830 slew-rate = <1>;
835 bias-disable;
839 /omit-if-no-ref/
840 spi5_sleep_pins_a: spi5-sleep-0 {
842 pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
848 /omit-if-no-ref/
849 stm32g0_intn_pins_a: stm32g0-intn-0 {
852 bias-pull-up;
856 /omit-if-no-ref/
857 uart4_pins_a: uart4-0 {
859 pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
860 bias-disable;
861 drive-push-pull;
862 slew-rate = <0>;
866 bias-disable;
870 /omit-if-no-ref/
871 uart4_idle_pins_a: uart4-idle-0 {
873 pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
877 bias-disable;
881 /omit-if-no-ref/
882 uart4_sleep_pins_a: uart4-sleep-0 {
884 pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
889 /omit-if-no-ref/
890 uart4_pins_b: uart4-1 {
893 bias-disable;
894 drive-push-pull;
895 slew-rate = <0>;
899 bias-pull-up;
903 /omit-if-no-ref/
904 uart4_idle_pins_b: uart4-idle-1 {
910 bias-pull-up;
914 /omit-if-no-ref/
915 uart4_sleep_pins_b: uart4-sleep-1 {
922 /omit-if-no-ref/
923 uart7_pins_a: uart7-0 {
927 bias-disable;
928 drive-push-pull;
929 slew-rate = <0>;
932 pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */
933 <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */
934 bias-disable;
938 /omit-if-no-ref/
939 uart7_idle_pins_a: uart7-idle-0 {
942 <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
946 bias-disable;
947 drive-push-pull;
948 slew-rate = <0>;
951 pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */
952 bias-disable;
956 /omit-if-no-ref/
957 uart7_sleep_pins_a: uart7-sleep-0 {
961 <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */
962 <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
966 /omit-if-no-ref/
967 uart8_pins_a: uart8-0 {
969 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
970 bias-disable;
971 drive-push-pull;
972 slew-rate = <0>;
976 bias-pull-up;
980 /omit-if-no-ref/
981 uart8_idle_pins_a: uart8-idle-0 {
983 pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
987 bias-pull-up;
991 /omit-if-no-ref/
992 uart8_sleep_pins_a: uart8-sleep-0 {
994 pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
999 /omit-if-no-ref/
1000 usart1_pins_a: usart1-0 {
1004 bias-disable;
1005 drive-push-pull;
1006 slew-rate = <0>;
1010 <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
1011 bias-pull-up;
1015 /omit-if-no-ref/
1016 usart1_idle_pins_a: usart1-idle-0 {
1019 <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
1023 bias-disable;
1024 drive-push-pull;
1025 slew-rate = <0>;
1029 bias-pull-up;
1033 /omit-if-no-ref/
1034 usart1_sleep_pins_a: usart1-sleep-0 {
1038 <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
1043 /omit-if-no-ref/
1044 usart1_pins_b: usart1-1 {
1047 bias-disable;
1048 drive-push-pull;
1049 slew-rate = <0>;
1053 bias-pull-up;
1057 /omit-if-no-ref/
1058 usart1_idle_pins_b: usart1-idle-1 {
1064 bias-pull-up;
1068 /omit-if-no-ref/
1069 usart1_sleep_pins_b: usart1-sleep-1 {
1076 /omit-if-no-ref/
1077 usart2_pins_a: usart2-0 {
1081 bias-disable;
1082 drive-push-pull;
1083 slew-rate = <0>;
1087 <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
1088 bias-disable;
1092 /omit-if-no-ref/
1093 usart2_idle_pins_a: usart2-idle-0 {
1096 <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
1100 bias-disable;
1101 drive-push-pull;
1102 slew-rate = <0>;
1106 bias-disable;
1110 /omit-if-no-ref/
1111 usart2_sleep_pins_a: usart2-sleep-0 {
1116 <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
1120 /omit-if-no-ref/
1121 usart2_pins_b: usart2-1 {
1125 bias-disable;
1126 drive-push-pull;
1127 slew-rate = <0>;
1131 <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */
1132 bias-disable;
1136 /omit-if-no-ref/
1137 usart2_idle_pins_b: usart2-idle-1 {
1140 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
1144 bias-disable;
1145 drive-push-pull;
1146 slew-rate = <0>;
1150 bias-disable;
1154 /omit-if-no-ref/
1155 usart2_sleep_pins_b: usart2-sleep-1 {
1160 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */