Lines Matching +full:1 +full:c00

48 	#address-cells = <1>;
49 	#size-cells = <1>;
79 			#address-cells = <1>;
93 			timer@1 {
95 				reg = <1>;
101 			#address-cells = <1>;
123 			#address-cells = <1>;
144 		timers5: timers@40000c00 {
145 			#address-cells = <1>;
167 			#address-cells = <1>;
183 			#address-cells = <1>;
199 			#address-cells = <1>;
220 		timers13: timers@40001c00 {
251 			clocks = <&rcc 1 CLK_RTC>;
252 			assigned-clocks = <&rcc 1 CLK_RTC>;
253 			assigned-clock-parents = <&rcc 1 CLK_LSE>;
255 			interrupts = <17 1>;
261 			#address-cells = <1>;
270 		spi3: spi@40003c00 {
271 			#address-cells = <1>;
284 			clocks = <&rcc 1 CLK_USART2>;
292 			clocks = <&rcc 1 CLK_USART3>;
296 		usart4: serial@40004c00 {
300 			clocks = <&rcc 1 CLK_UART4>;
308 			clocks = <&rcc 1 CLK_UART5>;
318 			clocks = <&rcc 1 CLK_I2C1>;
319 			#address-cells = <1>;
330 			clocks = <&rcc 1 CLK_I2C2>;
331 			#address-cells = <1>;
336 		i2c3: i2c@40005c00 {
342 			clocks = <&rcc 1 CLK_I2C3>;
343 			#address-cells = <1>;
354 			clocks = <&rcc 1 CLK_I2C4>;
355 			#address-cells = <1>;
390 		cec: cec@40006c00 {
394 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
403 			clocks = <&rcc 1 CLK_UART7>;
407 		usart8: serial@40007c00 {
411 			clocks = <&rcc 1 CLK_UART8>;
416 			#address-cells = <1>;
438 			#address-cells = <1>;
463 			clocks = <&rcc 1 CLK_USART1>;
471 			clocks = <&rcc 1 CLK_USART6>;
475 		sdio2: mmc@40011c00 {
486 		sdio1: mmc@40012c00 {
498 			#address-cells = <1>;
508 			#address-cells = <1>;
523 		exti: interrupt-controller@40013c00 {
528 			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
532 			#address-cells = <1>;
582 			#address-cells = <1>;
592 			#address-cells = <1>;
606 			clocks = <&rcc 1 CLK_LCD>;
624 			#reset-cells = <1>;
630 			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
691 	clocks = <&rcc 1 0>;