Lines Matching +full:0 +full:x40020000
15 ranges = <0 0x40020000 0x3000>;
17 st,syscfg = <&syscfg 0x8>;
24 reg = <0x0 0x400>;
25 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
34 reg = <0x400 0x400>;
35 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
44 reg = <0x800 0x400>;
45 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
54 reg = <0xc00 0x400>;
55 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
64 reg = <0x1000 0x400>;
65 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
74 reg = <0x1400 0x400>;
75 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
84 reg = <0x1800 0x400>;
85 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
94 reg = <0x1c00 0x400>;
95 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
104 reg = <0x2000 0x400>;
105 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
114 reg = <0x2400 0x400>;
115 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
124 reg = <0x2800 0x400>;
125 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
129 cec_pins_a: cec-0 {
132 slew-rate = <0>;
138 usart1_pins_a: usart1-0 {
143 slew-rate = <0>;
156 slew-rate = <0>;
164 i2c1_pins_b: i2c1-0 {
170 slew-rate = <0>;
174 i2c3_pins_a: i2c3-0 {
180 slew-rate = <0>;
184 usbotg_hs_pins_a: usbotg-hs-0 {
188 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
191 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
208 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
211 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
224 usbotg_fs_pins_a: usbotg-fs-0 {
235 sdio_pins_a: sdio-pins-a-0 {
248 sdio_pins_od_a: sdio-pins-od-a-0 {
266 sdio_pins_sleep_a: sdio-pins-sleep-a-0 {
277 sdio_pins_b: sdio-pins-b-0 {
290 sdio_pins_od_b: sdio-pins-od-b-0 {
308 sdio_pins_sleep_b: sdio-pins-sleep-b-0 {
319 can1_pins_a: can1-0 {
344 pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
361 can2_pins_a: can2-0 {
381 can3_pins_a: can3-0 {
401 ltdc_pins_a: ltdc-0 {
409 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
424 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */