Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:b
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
7 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
8 #include <dt-bindings/mfd/stm32f7-rcc.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
15 ranges = <0 0x40020000 0x3000>;
16 interrupt-parent = <&exti>;
17 st,syscfg = <&syscfg 0x8>;
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
24 reg = <0x0 0x400>;
25 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
26 st,bank-name = "GPIOA";
30 gpio-controller;
31 #gpio-cells = <2>;
32 interrupt-controller;
33 #interrupt-cells = <2>;
34 reg = <0x400 0x400>;
35 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
36 st,bank-name = "GPIOB";
40 gpio-controller;
41 #gpio-cells = <2>;
42 interrupt-controller;
43 #interrupt-cells = <2>;
44 reg = <0x800 0x400>;
45 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
46 st,bank-name = "GPIOC";
50 gpio-controller;
51 #gpio-cells = <2>;
52 interrupt-controller;
53 #interrupt-cells = <2>;
54 reg = <0xc00 0x400>;
55 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
56 st,bank-name = "GPIOD";
60 gpio-controller;
61 #gpio-cells = <2>;
62 interrupt-controller;
63 #interrupt-cells = <2>;
64 reg = <0x1000 0x400>;
65 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
66 st,bank-name = "GPIOE";
70 gpio-controller;
71 #gpio-cells = <2>;
72 interrupt-controller;
73 #interrupt-cells = <2>;
74 reg = <0x1400 0x400>;
75 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
76 st,bank-name = "GPIOF";
80 gpio-controller;
81 #gpio-cells = <2>;
82 interrupt-controller;
83 #interrupt-cells = <2>;
84 reg = <0x1800 0x400>;
85 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
86 st,bank-name = "GPIOG";
90 gpio-controller;
91 #gpio-cells = <2>;
92 interrupt-controller;
93 #interrupt-cells = <2>;
94 reg = <0x1c00 0x400>;
95 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
96 st,bank-name = "GPIOH";
100 gpio-controller;
101 #gpio-cells = <2>;
102 interrupt-controller;
103 #interrupt-cells = <2>;
104 reg = <0x2000 0x400>;
105 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
106 st,bank-name = "GPIOI";
110 gpio-controller;
111 #gpio-cells = <2>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
114 reg = <0x2400 0x400>;
115 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
116 st,bank-name = "GPIOJ";
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 reg = <0x2800 0x400>;
125 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
126 st,bank-name = "GPIOK";
129 cec_pins_a: cec-0 {
131 pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
132 slew-rate = <0>;
133 drive-open-drain;
134 bias-disable;
138 usart1_pins_a: usart1-0 {
140 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
141 bias-disable;
142 drive-push-pull;
143 slew-rate = <0>;
146 pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
147 bias-disable;
151 usart1_pins_b: usart1-1 {
153 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
154 bias-disable;
155 drive-push-pull;
156 slew-rate = <0>;
159 pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
160 bias-disable;
164 i2c1_pins_b: i2c1-0 {
166 pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
167 <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
168 bias-disable;
169 drive-open-drain;
170 slew-rate = <0>;
174 i2c3_pins_a: i2c3-0 {
178 bias-disable;
179 drive-open-drain;
180 slew-rate = <0>;
184 usbotg_hs_pins_a: usbotg-hs-0 {
188 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
189 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
190 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
191 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
192 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
193 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
194 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
195 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
196 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
197 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
198 bias-disable;
199 drive-push-pull;
200 slew-rate = <2>;
204 usbotg_hs_pins_b: usbotg-hs-1 {
208 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
209 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
210 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
211 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
212 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
213 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
214 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
215 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
216 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
217 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
218 bias-disable;
219 drive-push-pull;
220 slew-rate = <2>;
224 usbotg_fs_pins_a: usbotg-fs-0 {
226 pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
227 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
228 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
229 bias-disable;
230 drive-push-pull;
231 slew-rate = <2>;
235 sdio_pins_a: sdio-pins-a-0 {
238 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
243 drive-push-pull;
244 slew-rate = <2>;
248 sdio_pins_od_a: sdio-pins-od-a-0 {
251 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
255 drive-push-pull;
256 slew-rate = <2>;
261 drive-open-drain;
262 slew-rate = <2>;
266 sdio_pins_sleep_a: sdio-pins-sleep-a-0 {
269 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1 D1 */
277 sdio_pins_b: sdio-pins-b-0 {
279 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
281 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
282 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
285 drive-push-pull;
286 slew-rate = <2>;
290 sdio_pins_od_b: sdio-pins-od-b-0 {
292 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
294 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
295 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
297 drive-push-pull;
298 slew-rate = <2>;
303 drive-open-drain;
304 slew-rate = <2>;
308 sdio_pins_sleep_b: sdio-pins-sleep-b-0 {
310 pinmux = <STM32_PINMUX('G', 9, ANALOG)>, /* SDMMC2 D0 */
312 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2 D2 */
313 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2 D3 */
319 can1_pins_a: can1-0 {
321 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
324 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
325 bias-pull-up;
329 can1_pins_b: can1-1 {
331 pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
334 pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
335 bias-pull-up;
339 can1_pins_c: can1-2 {
344 pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
345 bias-pull-up;
350 can1_pins_d: can1-3 {
356 bias-pull-up;
361 can2_pins_a: can2-0 {
363 pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
366 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
367 bias-pull-up;
371 can2_pins_b: can2-1 {
373 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
376 pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
377 bias-pull-up;
381 can3_pins_a: can3-0 {
383 pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
386 pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
387 bias-pull-up;
391 can3_pins_b: can3-1 {
393 pinmux = <STM32_PINMUX('B', 4, AF11)>; /* CAN3_TX */
396 pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
397 bias-pull-up;
401 ltdc_pins_a: ltdc-0 {
405 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
409 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
418 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
424 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
431 slew-rate = <2>;