Lines Matching +full:0 +full:x40020000
51 ranges = <0 0x40020000 0x3000>;
53 st,syscfg = <&syscfg 0x8>;
60 reg = <0x0 0x400>;
61 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
70 reg = <0x400 0x400>;
71 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
80 reg = <0x800 0x400>;
81 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
90 reg = <0xc00 0x400>;
91 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
100 reg = <0x1000 0x400>;
101 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
110 reg = <0x1400 0x400>;
111 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
120 reg = <0x1800 0x400>;
121 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
130 reg = <0x1c00 0x400>;
131 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
140 reg = <0x2000 0x400>;
141 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
150 reg = <0x2400 0x400>;
151 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
160 reg = <0x2800 0x400>;
161 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
165 usart1_pins_a: usart1-0 {
170 slew-rate = <0>;
178 usart3_pins_a: usart3-0 {
183 slew-rate = <0>;
191 usbotg_fs_pins_a: usbotg-fs-0 {
213 usbotg_hs_pins_a: usbotg-hs-0 {
217 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
220 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
233 ethernet_mii: mii-0 {
259 pwm1_pins: pwm1-0 {
267 pwm3_pins: pwm3-0 {
274 i2c1_pins: i2c1-0 {
284 ltdc_pins_a: ltdc-0 {
290 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
306 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
328 <STM32_PINMUX('B', 0, AF9)>,
368 spi5_pins: spi5-0 {
376 slew-rate = <0>;
385 i2c3_pins: i2c3-0 {
397 dcmi_pins: dcmi-0 {
420 sdio_pins: sdio-pins-0 {
433 sdio_pins_od: sdio-pins-od-0 {
451 can1_pins_a: can1-0 {
461 can2_pins_a: can2-0 {