Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:b
2 * Copyright 2017 - Alexandre Torgue <[email protected]>
4 * This file is dual-licensed: you can use it either under the terms
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
44 #include <dt-bindings/mfd/stm32f4-rcc.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges = <0 0x40020000 0x3000>;
52 interrupt-parent = <&exti>;
53 st,syscfg = <&syscfg 0x8>;
56 gpio-controller;
57 #gpio-cells = <2>;
58 interrupt-controller;
59 #interrupt-cells = <2>;
60 reg = <0x0 0x400>;
61 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
62 st,bank-name = "GPIOA";
66 gpio-controller;
67 #gpio-cells = <2>;
68 interrupt-controller;
69 #interrupt-cells = <2>;
70 reg = <0x400 0x400>;
71 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
72 st,bank-name = "GPIOB";
76 gpio-controller;
77 #gpio-cells = <2>;
78 interrupt-controller;
79 #interrupt-cells = <2>;
80 reg = <0x800 0x400>;
81 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
82 st,bank-name = "GPIOC";
86 gpio-controller;
87 #gpio-cells = <2>;
88 interrupt-controller;
89 #interrupt-cells = <2>;
90 reg = <0xc00 0x400>;
91 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
92 st,bank-name = "GPIOD";
96 gpio-controller;
97 #gpio-cells = <2>;
98 interrupt-controller;
99 #interrupt-cells = <2>;
100 reg = <0x1000 0x400>;
101 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
102 st,bank-name = "GPIOE";
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
110 reg = <0x1400 0x400>;
111 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
112 st,bank-name = "GPIOF";
116 gpio-controller;
117 #gpio-cells = <2>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 reg = <0x1800 0x400>;
121 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
122 st,bank-name = "GPIOG";
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <2>;
130 reg = <0x1c00 0x400>;
131 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
132 st,bank-name = "GPIOH";
136 gpio-controller;
137 #gpio-cells = <2>;
138 interrupt-controller;
139 #interrupt-cells = <2>;
140 reg = <0x2000 0x400>;
141 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
142 st,bank-name = "GPIOI";
146 gpio-controller;
147 #gpio-cells = <2>;
148 interrupt-controller;
149 #interrupt-cells = <2>;
150 reg = <0x2400 0x400>;
151 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
152 st,bank-name = "GPIOJ";
156 gpio-controller;
157 #gpio-cells = <2>;
158 interrupt-controller;
159 #interrupt-cells = <2>;
160 reg = <0x2800 0x400>;
161 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
162 st,bank-name = "GPIOK";
165 usart1_pins_a: usart1-0 {
167 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
168 bias-disable;
169 drive-push-pull;
170 slew-rate = <0>;
173 pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
174 bias-disable;
178 usart3_pins_a: usart3-0 {
180 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
181 bias-disable;
182 drive-push-pull;
183 slew-rate = <0>;
186 pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
187 bias-disable;
191 usbotg_fs_pins_a: usbotg-fs-0 {
193 pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
194 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
195 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
196 bias-disable;
197 drive-push-pull;
198 slew-rate = <2>;
202 usbotg_fs_pins_b: usbotg-fs-1 {
204 pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
205 <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
206 <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
207 bias-disable;
208 drive-push-pull;
209 slew-rate = <2>;
213 usbotg_hs_pins_a: usbotg-hs-0 {
217 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
218 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
219 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
220 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
221 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
222 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
223 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
224 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
225 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
226 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
227 bias-disable;
228 drive-push-pull;
229 slew-rate = <2>;
233 ethernet_mii: mii-0 {
238 <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
241 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
243 <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
244 <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
249 slew-rate = <2>;
253 adc3_in8_pin: adc-200 {
259 pwm1_pins: pwm1-0 {
261 pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
262 <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
263 <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
267 pwm3_pins: pwm3-0 {
269 pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
270 <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
274 i2c1_pins: i2c1-0 {
276 pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
277 <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
278 bias-disable;
279 drive-open-drain;
280 slew-rate = <3>;
284 ltdc_pins_a: ltdc-0 {
290 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
299 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
306 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
314 slew-rate = <2>;
318 ltdc_pins_b: ltdc-1 {
322 <STM32_PINMUX('A', 4, AF14)>,
328 <STM32_PINMUX('B', 0, AF9)>,
330 <STM32_PINMUX('A', 11, AF14)>,
332 <STM32_PINMUX('A', 12, AF14)>,
334 <STM32_PINMUX('B', 1, AF9)>,
338 <STM32_PINMUX('A', 6, AF14)>,
342 <STM32_PINMUX('B', 10, AF14)>,
348 <STM32_PINMUX('B', 11, AF14)>,
356 <STM32_PINMUX('A', 3, AF14)>,
358 <STM32_PINMUX('B', 8, AF14)>,
360 <STM32_PINMUX('B', 9, AF14)>,
364 slew-rate = <2>;
368 spi5_pins: spi5-0 {
372 <STM32_PINMUX('F', 9, AF5)>;
374 bias-disable;
375 drive-push-pull;
376 slew-rate = <0>;
381 bias-disable;
385 i2c3_pins: i2c3-0 {
387 pinmux = <STM32_PINMUX('C', 9, AF4)>,
389 <STM32_PINMUX('A', 8, AF4)>;
391 bias-disable;
392 drive-open-drain;
393 slew-rate = <3>;
397 dcmi_pins: dcmi-0 {
399 pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
400 <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
401 <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
405 <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
408 <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
414 bias-disable;
415 drive-push-pull;
416 slew-rate = <3>;
420 sdio_pins: sdio-pins-0 {
423 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
428 drive-push-pull;
429 slew-rate = <2>;
433 sdio_pins_od: sdio-pins-od-0 {
436 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
440 drive-push-pull;
441 slew-rate = <2>;
446 drive-open-drain;
447 slew-rate = <2>;
451 can1_pins_a: can1-0 {
453 pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
456 pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
457 bias-pull-up;
461 can2_pins_a: can2-0 {
463 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
466 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
467 bias-pull-up;
471 can2_pins_b: can2-1 {
473 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
476 pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
477 bias-pull-up;