Lines Matching +full:0 +full:x425
20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
44 reg = <0xf0000200 0x100>;
51 reg = <0xf0000600 0x20>;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
66 reg = <0xf0100000 0x1000>;
78 reg = <0xfb400000 0x400>;
87 reg = <0xfe400000 0x400>;
103 reg = <0xe6138000 0x200>;
115 reg = <0xe6900000 4>,
116 <0xe6900010 4>,
117 <0xe6900020 1>,
118 <0xe6900040 1>,
119 <0xe6900060 1>;
137 reg = <0xe6900004 4>,
138 <0xe6900014 4>,
139 <0xe6900024 1>,
140 <0xe6900044 1>,
141 <0xe6900064 1>;
159 reg = <0xe6900008 4>,
160 <0xe6900018 4>,
161 <0xe6900028 1>,
162 <0xe6900048 1>,
163 <0xe6900068 1>;
181 reg = <0xe690000c 4>,
182 <0xe690001c 4>,
183 <0xe690002c 1>,
184 <0xe690004c 1>,
185 <0xe690006c 1>;
201 #size-cells = <0>;
203 reg = <0xe6820000 0x425>;
215 #size-cells = <0>;
217 reg = <0xe6822000 0x425>;
229 #size-cells = <0>;
231 reg = <0xe6824000 0x425>;
243 #size-cells = <0>;
245 reg = <0xe6826000 0x425>;
257 #size-cells = <0>;
259 reg = <0xe6828000 0x425>;
271 reg = <0xe6bd0000 0x100>;
281 reg = <0xe6e20000 0x0064>;
286 #size-cells = <0>;
292 reg = <0xe6e10000 0x0064>;
297 #size-cells = <0>;
303 reg = <0xe6e00000 0x0064>;
308 #size-cells = <0>;
314 reg = <0xe6c90000 0x0064>;
319 #size-cells = <0>;
325 reg = <0xee100000 0x100>;
338 reg = <0xee120000 0x100>;
350 reg = <0xee140000 0x100>;
362 reg = <0xe6c40000 0x100>;
372 reg = <0xe6c50000 0x100>;
382 reg = <0xe6c60000 0x100>;
392 reg = <0xe6c70000 0x100>;
402 reg = <0xe6c80000 0x100>;
412 reg = <0xe6cb0000 0x100>;
422 reg = <0xe6cc0000 0x100>;
432 reg = <0xe6cd0000 0x100>;
442 reg = <0xe6c30000 0x100>;
452 reg = <0xe6050000 0x8000>,
453 <0xe605801c 0x1c>;
457 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
460 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
461 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
462 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
463 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
464 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
465 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
466 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
467 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
473 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
478 #size-cells = <0>;
479 #power-domain-cells = <0>;
481 pd_c4: c4@0 {
482 reg = <0>;
483 #power-domain-cells = <0>;
488 #power-domain-cells = <0>;
493 #power-domain-cells = <0>;
498 #power-domain-cells = <0>;
503 #power-domain-cells = <0>;
508 #power-domain-cells = <0>;
514 #size-cells = <0>;
515 #power-domain-cells = <0>;
519 #power-domain-cells = <0>;
524 #power-domain-cells = <0>;
531 #size-cells = <0>;
532 #power-domain-cells = <0>;
537 #size-cells = <0>;
538 #power-domain-cells = <0>;
543 #size-cells = <0>;
544 #power-domain-cells = <0>;
552 #size-cells = <0>;
553 #power-domain-cells = <0>;
557 #power-domain-cells = <0>;
562 #power-domain-cells = <0>;
568 #size-cells = <0>;
569 #power-domain-cells = <0>;
573 #power-domain-cells = <0>;
584 reg = <0xec230000 0x400>;
585 interrupts = <GIC_SPI 146 0x4>;
596 ranges = <0 0 0x20000000>;
597 reg = <0xfec10000 0x400>;
611 #clock-cells = <0>;
616 #clock-cells = <0>;
621 #clock-cells = <0>;
623 clock-frequency = <0>;
627 #clock-cells = <0>;
629 clock-frequency = <0>;
633 #clock-cells = <0>;
635 clock-frequency = <0>;
639 #clock-cells = <0>;
641 clock-frequency = <0>;
647 reg = <0xe6150000 0x10000>;
659 reg = <0xe6150008 4>;
663 <0>;
664 #clock-cells = <0>;
668 reg = <0xe615000c 4>;
672 <0>;
673 #clock-cells = <0>;
677 reg = <0xe615001c 4>;
681 <0>;
682 #clock-cells = <0>;
686 reg = <0xe6150010 4>;
687 clocks = <&pll1_div2_clk>, <0>,
688 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
689 #clock-cells = <0>;
694 reg = <0xe6150014 4>;
695 clocks = <&pll1_div2_clk>, <0>,
696 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
697 #clock-cells = <0>;
701 reg = <0xe6150074 4>;
703 <&pll1_div13_clk>, <0>;
704 #clock-cells = <0>;
708 reg = <0xe6150078 4>;
710 <&pll1_div13_clk>, <0>;
711 #clock-cells = <0>;
715 reg = <0xe615007c 4>;
717 <&pll1_div13_clk>, <0>;
718 #clock-cells = <0>;
722 reg = <0xe6150018 4>;
725 #clock-cells = <0>;
729 reg = <0xe6150090 4>;
732 #clock-cells = <0>;
736 reg = <0xe6150080 4>;
739 #clock-cells = <0>;
743 reg = <0xe6150084 4>;
746 #clock-cells = <0>;
750 reg = <0xe6150094 4>;
753 #clock-cells = <0>;
757 reg = <0xe6150088 4>;
758 clocks = <&pll1_div2_clk>, <0>,
759 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
760 #clock-cells = <0>;
764 reg = <0xe615008c 4>;
766 <&pll1_div7_clk>, <0>;
767 #clock-cells = <0>;
771 reg = <0xe6150098 4>;
772 clocks = <&pll1_div2_clk>, <0>,
773 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
774 #clock-cells = <0>;
778 reg = <0xe615009c 4>;
779 clocks = <&pll1_div2_clk>, <0>,
780 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
781 #clock-cells = <0>;
785 reg = <0xe6150060 4>;
786 clocks = <&pll1_div2_clk>, <0>,
787 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
788 #clock-cells = <0>;
792 reg = <0xe6150064 4>;
795 <&extcki_clk>, <0>, <0>, <0>;
796 #clock-cells = <0>;
803 #clock-cells = <0>;
810 #clock-cells = <0>;
817 #clock-cells = <0>;
824 #clock-cells = <0>;
831 #clock-cells = <0>;
839 reg = <0xe6150130 4>, <0xe6150030 4>;
850 reg = <0xe6150134 4>, <0xe6150038 4>;
873 reg = <0xe6150138 4>, <0xe6150040 4>;
897 reg = <0xe615013c 4>, <0xe6150048 4>;
925 reg = <0xe6150140 4>, <0xe615004c 4>;
938 reg = <0xe6150144 4>, <0xe615003c 4>;