Lines Matching +full:0 +full:xe61f0200
21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 L2_CA15: cache-controller-0 {
66 reg = <0 0xe61e0000 0 0x30>;
79 reg = <0 0xfff80000 0 0x30>;
92 reg = <0 0xe6790000 0 0x10000>;
98 reg = <0 0xe67a0000 0 0x10000>;
104 #size-cells = <0>;
106 reg = <0 0xe60b0000 0 0x428>;
116 reg = <0 0xe6130000 0 0x1004>;
135 reg = <0 0xe61c0000 0 0x200>;
136 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
176 reg = <0 0xe61c0200 0 0x200>;
209 reg = <0 0xe6050000 0 0x9000>;
213 <&pfc 0 0 31>, <&pfc 32 32 9>,
220 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
221 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
222 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
223 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
224 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
225 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
226 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
227 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
228 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
229 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
230 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
231 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
232 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
233 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
234 <&irqc1 24 0>, <&irqc1 25 0>;
240 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
241 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
249 #size-cells = <0>;
251 reg = <0 0xe6500000 0 0x428>;
260 #size-cells = <0>;
262 reg = <0 0xe6510000 0 0x428>;
271 #size-cells = <0>;
273 reg = <0 0xe6520000 0 0x428>;
282 #size-cells = <0>;
284 reg = <0 0xe6530000 0 0x428>;
293 #size-cells = <0>;
295 reg = <0 0xe6540000 0 0x428>;
304 #size-cells = <0>;
306 reg = <0 0xe6550000 0 0x428>;
315 #size-cells = <0>;
317 reg = <0 0xe6560000 0 0x428>;
326 #size-cells = <0>;
328 reg = <0 0xe6570000 0 0x428>;
337 reg = <0 0xe6c20000 0 0x100>;
347 reg = <0 0xe6c30000 0 0x100>;
357 reg = <0 0xe6c40000 0 0x100>;
367 reg = <0 0xe6c50000 0 0x100>;
377 reg = <0 0xe6ce0000 0 0x100>;
387 reg = <0 0xe6cf0000 0 0x100>;
397 reg = <0 0xee100000 0 0x100>;
407 reg = <0 0xee120000 0 0x100>;
417 reg = <0 0xee140000 0 0x100>;
427 reg = <0 0xee200000 0 0x80>;
436 reg = <0 0xee220000 0 0x80>;
446 #address-cells = <0>;
448 reg = <0 0xf1001000 0 0x1000>,
449 <0 0xf1002000 0 0x2000>,
450 <0 0xf1004000 0 0x2000>,
451 <0 0xf1006000 0 0x2000>;
463 ranges = <0 0 0 0x20000000>;
464 reg = <0 0xfec10000 0 0x400>;
477 #clock-cells = <0>;
479 clock-frequency = <0>;
483 #clock-cells = <0>;
485 clock-frequency = <0>;
489 #clock-cells = <0>;
491 clock-frequency = <0>;
495 #clock-cells = <0>;
497 clock-frequency = <0>;
501 #clock-cells = <0>;
503 clock-frequency = <0>;
509 reg = <0 0xe6150000 0 0x10000>;
521 reg = <0 0xe6150010 0 4>;
522 clocks = <&pll1_div2_clk>, <0>,
523 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
524 #clock-cells = <0>;
529 reg = <0 0xe6150074 0 4>;
531 <0>, <&extal2_clk>;
532 #clock-cells = <0>;
536 reg = <0 0xe6150078 0 4>;
538 <0>, <&extal2_clk>;
539 #clock-cells = <0>;
543 reg = <0 0xe615007c 0 4>;
545 <0>, <&extal2_clk>;
546 #clock-cells = <0>;
550 reg = <0 0xe6150240 0 4>;
552 <0>, <&extal2_clk>;
553 #clock-cells = <0>;
557 reg = <0 0xe6150244 0 4>;
559 <0>, <&extal2_clk>;
560 #clock-cells = <0>;
564 reg = <0 0xe6150008 0 4>;
566 <0>, <&extal2_clk>, <&main_div2_clk>,
567 <&extalr_clk>, <0>, <0>;
568 #clock-cells = <0>;
572 reg = <0 0xe615000c 0 4>;
574 <0>, <&extal2_clk>, <&main_div2_clk>,
575 <&extalr_clk>, <0>, <0>;
576 #clock-cells = <0>;
580 reg = <0 0xe615001c 0 4>;
582 <0>, <&extal2_clk>, <&main_div2_clk>,
583 <&extalr_clk>, <0>, <0>;
584 #clock-cells = <0>;
588 reg = <0 0xe6150014 0 4>;
590 <0>, <&extal2_clk>, <&main_div2_clk>,
591 <&extalr_clk>, <0>, <0>;
592 #clock-cells = <0>;
596 reg = <0 0xe6150034 0 4>;
598 <0>, <&extal2_clk>, <&main_div2_clk>,
599 <&extalr_clk>, <0>, <0>;
600 #clock-cells = <0>;
604 reg = <0 0xe6150018 0 4>;
606 <&fsiack_clk>, <0>;
607 #clock-cells = <0>;
611 reg = <0 0xe6150090 0 4>;
613 <&fsibck_clk>, <0>;
614 #clock-cells = <0>;
618 reg = <0 0xe6150080 0 4>;
621 #clock-cells = <0>;
625 reg = <0 0xe6150098 0 4>;
627 #clock-cells = <0>;
631 reg = <0 0xe615026c 0 4>;
633 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
634 #clock-cells = <0>;
638 reg = <0 0xe6150094 0 4>;
641 #clock-cells = <0>;
648 #clock-cells = <0>;
655 #clock-cells = <0>;
662 #clock-cells = <0>;
669 #clock-cells = <0>;
676 #clock-cells = <0>;
684 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
695 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
711 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
734 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
749 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
762 reg = <0 0xff000044 0 4>;
767 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
772 #size-cells = <0>;
773 #power-domain-cells = <0>;
775 pd_c4: c4@0 {
776 reg = <0>;
778 #size-cells = <0>;
779 #power-domain-cells = <0>;
783 #power-domain-cells = <0>;
788 #power-domain-cells = <0>;
794 #size-cells = <0>;
795 #power-domain-cells = <0>;
799 #power-domain-cells = <0>;
806 #size-cells = <0>;
807 #power-domain-cells = <0>;
811 #power-domain-cells = <0>;
818 #size-cells = <0>;
819 #power-domain-cells = <0>;
823 #power-domain-cells = <0>;
830 #power-domain-cells = <0>;
835 #power-domain-cells = <0>;
840 #power-domain-cells = <0>;
846 #size-cells = <0>;
847 #power-domain-cells = <0>;
851 #power-domain-cells = <0>;
857 #power-domain-cells = <0>;
862 #power-domain-cells = <0>;
868 #size-cells = <0>;
869 #power-domain-cells = <0>;
873 #power-domain-cells = <0>;
878 #power-domain-cells = <0>;
884 #power-domain-cells = <0>;
890 #size-cells = <0>;
891 #power-domain-cells = <0>;
895 #power-domain-cells = <0>;
900 #power-domain-cells = <0>;