Lines Matching refs:gcc
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
204 gcc: clock-controller@100000 { label
205 compatible = "qcom,gcc-sdx65";
226 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
238 resets = <&gcc GCC_QUSB2PHY_BCR>;
246 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
247 <&gcc GCC_USB3_PRIM_CLKREF_EN>,
248 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
249 <&gcc GCC_USB3_PHY_PIPE_CLK>;
258 resets = <&gcc GCC_USB3_PHY_BCR>,
259 <&gcc GCC_USB3PHY_PHY_BCR>;
319 clocks = <&gcc GCC_PCIE_AUX_CLK>,
320 <&gcc GCC_PCIE_CFG_AHB_CLK>,
321 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
322 <&gcc GCC_PCIE_SLV_AXI_CLK>,
323 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
324 <&gcc GCC_PCIE_SLEEP_CLK>,
325 <&gcc GCC_PCIE_0_CLKREF_EN>;
342 resets = <&gcc GCC_PCIE_BCR>;
345 power-domains = <&gcc PCIE_GDSC>;
361 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
362 <&gcc GCC_PCIE_CFG_AHB_CLK>,
363 <&gcc GCC_PCIE_0_CLKREF_EN>,
364 <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
365 <&gcc GCC_PCIE_PIPE_CLK>;
372 resets = <&gcc GCC_PCIE_PHY_BCR>;
375 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
378 power-domains = <&gcc PCIE_GDSC>;
477 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
478 <&gcc GCC_SDCC1_APPS_CLK>;
497 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
498 <&gcc GCC_USB30_MASTER_CLK>,
499 <&gcc GCC_USB30_MSTR_AXI_CLK>,
500 <&gcc GCC_USB30_SLEEP_CLK>,
501 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
505 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
506 <&gcc GCC_USB30_MASTER_CLK>;
520 power-domains = <&gcc USB30_GDSC>;
522 resets = <&gcc GCC_USB30_BCR>;
655 compatible = "qcom,sdx55-apcs-gcc", "syscon";
658 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;