Lines Matching full:assigned

154 			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 			assigned-clock-rates = <24000000>;
166 			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 			assigned-clock-rates = <48000000>;
175 			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
263 			assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
264 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
287 			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
288 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
336 			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
337 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
338 			assigned-clock-rates = <48000000>;
349 			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
350 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
351 			assigned-clock-rates = <48000000>;
361 			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
362 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
363 			assigned-clock-rates = <48000000>;
373 			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
374 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
375 			assigned-clock-rates = <48000000>;