Lines Matching full:scg1
132 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
186 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
224 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
225 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
238 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
239 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
248 scg1: clock-controller@403e0000 { label
249 compatible = "fsl,imx7ulp-scg1";
264 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
272 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
273 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
274 <&scg1 IMX7ULP_CLK_DDR_DIV>,
275 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
276 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
277 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
278 <&scg1 IMX7ULP_CLK_UPLL>,
279 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
280 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
281 <&scg1 IMX7ULP_CLK_ROSC>,
282 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
288 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
295 clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
296 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
304 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
305 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
306 <&scg1 IMX7ULP_CLK_DDR_DIV>,
307 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
308 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
309 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
310 <&scg1 IMX7ULP_CLK_UPLL>,
311 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
312 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
313 <&scg1 IMX7ULP_CLK_ROSC>,
314 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
334 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
337 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
347 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
350 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
362 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
374 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
462 clocks = <&scg1 IMX7ULP_CLK_DUMMY>;