Lines Matching +full:quadspi +full:- +full:memory
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
60 #address-cells = <1>;
61 #size-cells = <0>;
64 compatible = "arm,cortex-a9";
67 next-level-cache = <&L2>;
68 operating-points = <
75 fsl,soc-operating-points = <
82 clock-latency = <61036>; /* two CLK32 periods */
83 #cooling-cells = <2>;
89 clock-names = "arm", "pll2_pfd2_396m", "step",
91 arm-supply = <®_arm>;
92 soc-supply = <®_soc>;
93 nvmem-cells = <&cpu_speed_grade>;
94 nvmem-cell-names = "speed_grade";
98 ckil: clock-ckil {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
105 osc: clock-osc {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
112 ipp_di0: clock-ipp-di0 {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
116 clock-output-names = "ipp_di0";
119 ipp_di1: clock-ipp-di1 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 clock-output-names = "ipp_di1";
126 anaclk1: clock-anaclk1 {
127 compatible = "fixed-clock";
128 #clock-cells = <0>;
129 clock-frequency = <0>;
130 clock-output-names = "anaclk1";
133 anaclk2: clock-anaclk2 {
134 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 clock-frequency = <0>;
137 clock-output-names = "anaclk2";
141 compatible = "fsl,imx6sx-mqs";
147 compatible = "arm,cortex-a9-pmu";
148 interrupt-parent = <&gpc>;
153 compatible = "usb-nop-xceiv";
154 #phy-cells = <0>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160 compatible = "simple-bus";
161 interrupt-parent = <&gpc>;
165 compatible = "mmio-sram";
168 #address-cells = <1>;
169 #size-cells = <1>;
174 compatible = "mmio-sram";
177 #address-cells = <1>;
178 #size-cells = <1>;
182 intc: interrupt-controller@a01000 {
183 compatible = "arm,cortex-a9-gic";
184 #interrupt-cells = <3>;
185 interrupt-controller;
188 interrupt-parent = <&intc>;
191 L2: cache-controller@a02000 {
192 compatible = "arm,pl310-cache";
195 cache-unified;
196 cache-level = <2>;
197 arm,tag-latency = <4 2 3>;
198 arm,data-latency = <4 2 3>;
208 clock-names = "bus", "core", "shader";
209 power-domains = <&pd_pu>;
212 dma_apbh: dma-controller@1804000 {
213 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
219 #dma-cells = <1>;
220 dma-channels = <4>;
224 gpmi: nand-controller@1806000 {
225 compatible = "fsl,imx6sx-gpmi-nand";
226 #address-cells = <1>;
227 #size-cells = <1>;
229 reg-names = "gpmi-nand", "bch";
231 interrupt-names = "bch";
237 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
240 dma-names = "rx-tx";
245 compatible = "fsl,aips-bus", "simple-bus";
246 #address-cells = <1>;
247 #size-cells = <1>;
251 spba-bus@2000000 {
252 compatible = "fsl,spba-bus", "simple-bus";
253 #address-cells = <1>;
254 #size-cells = <1>;
259 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
264 dma-names = "rx", "tx";
272 clock-names = "core", "rxtx0",
281 #address-cells = <1>;
282 #size-cells = <0>;
283 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
288 clock-names = "ipg", "per";
293 #address-cells = <1>;
294 #size-cells = <0>;
295 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
300 clock-names = "ipg", "per";
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
312 clock-names = "ipg", "per";
317 #address-cells = <1>;
318 #size-cells = <0>;
319 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
324 clock-names = "ipg", "per";
329 compatible = "fsl,imx6sx-uart",
330 "fsl,imx6q-uart", "fsl,imx21-uart";
335 clock-names = "ipg", "per";
337 dma-names = "rx", "tx";
342 compatible = "fsl,imx35-esai";
349 clock-names = "core", "extal",
353 dma-names = "rx", "tx";
358 #sound-dai-cells = <0>;
359 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
364 clock-names = "ipg", "baud";
366 dma-names = "rx", "tx";
367 fsl,fifo-depth = <15>;
372 #sound-dai-cells = <0>;
373 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
378 clock-names = "ipg", "baud";
380 dma-names = "rx", "tx";
381 fsl,fifo-depth = <15>;
386 #sound-dai-cells = <0>;
387 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
392 clock-names = "ipg", "baud";
394 dma-names = "rx", "tx";
395 fsl,fifo-depth = <15>;
400 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
410 clock-names = "mem", "ipg", "asrck_0",
418 dma-names = "rxa", "rxb", "rxc",
420 fsl,asrc-rate = <48000>;
421 fsl,asrc-width = <16>;
427 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
432 clock-names = "ipg", "per";
433 #pwm-cells = <3>;
437 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
442 clock-names = "ipg", "per";
443 #pwm-cells = <3>;
447 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
452 clock-names = "ipg", "per";
453 #pwm-cells = <3>;
457 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
462 clock-names = "ipg", "per";
463 #pwm-cells = <3>;
467 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
472 clock-names = "ipg", "per";
473 fsl,stop-mode = <&gpr 0x10 1>;
478 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
483 clock-names = "ipg", "per";
484 fsl,stop-mode = <&gpr 0x10 2>;
489 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
494 clock-names = "ipg", "per";
498 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
502 gpio-controller;
503 #gpio-cells = <2>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 gpio-ranges = <&iomuxc 0 5 26>;
510 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
514 gpio-controller;
515 #gpio-cells = <2>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
518 gpio-ranges = <&iomuxc 0 31 20>;
522 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
526 gpio-controller;
527 #gpio-cells = <2>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
530 gpio-ranges = <&iomuxc 0 51 29>;
534 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
538 gpio-controller;
539 #gpio-cells = <2>;
540 interrupt-controller;
541 #interrupt-cells = <2>;
542 gpio-ranges = <&iomuxc 0 80 32>;
546 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
550 gpio-controller;
551 #gpio-cells = <2>;
552 interrupt-controller;
553 #interrupt-cells = <2>;
554 gpio-ranges = <&iomuxc 0 112 24>;
558 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
562 gpio-controller;
563 #gpio-cells = <2>;
564 interrupt-controller;
565 #interrupt-cells = <2>;
566 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
570 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
574 gpio-controller;
575 #gpio-cells = <2>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
578 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
582 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
590 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
597 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
604 clks: clock-controller@20c4000 {
605 compatible = "fsl,imx6sx-ccm";
609 #clock-cells = <1>;
611 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
615 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
616 "syscon", "simple-mfd";
622 reg_vdd1p1: regulator-1p1 {
623 compatible = "fsl,anatop-regulator";
624 regulator-name = "vdd1p1";
625 regulator-min-microvolt = <1000000>;
626 regulator-max-microvolt = <1200000>;
627 regulator-always-on;
628 anatop-reg-offset = <0x110>;
629 anatop-vol-bit-shift = <8>;
630 anatop-vol-bit-width = <5>;
631 anatop-min-bit-val = <4>;
632 anatop-min-voltage = <800000>;
633 anatop-max-voltage = <1375000>;
634 anatop-enable-bit = <0>;
637 reg_vdd3p0: regulator-3p0 {
638 compatible = "fsl,anatop-regulator";
639 regulator-name = "vdd3p0";
640 regulator-min-microvolt = <2625000>;
641 regulator-max-microvolt = <3400000>;
642 regulator-always-on;
643 anatop-reg-offset = <0x120>;
644 anatop-vol-bit-shift = <8>;
645 anatop-vol-bit-width = <5>;
646 anatop-min-bit-val = <0>;
647 anatop-min-voltage = <2625000>;
648 anatop-max-voltage = <3400000>;
649 anatop-enable-bit = <0>;
652 reg_vdd2p5: regulator-2p5 {
653 compatible = "fsl,anatop-regulator";
654 regulator-name = "vdd2p5";
655 regulator-min-microvolt = <2250000>;
656 regulator-max-microvolt = <2750000>;
657 regulator-always-on;
658 anatop-reg-offset = <0x130>;
659 anatop-vol-bit-shift = <8>;
660 anatop-vol-bit-width = <5>;
661 anatop-min-bit-val = <0>;
662 anatop-min-voltage = <2100000>;
663 anatop-max-voltage = <2875000>;
664 anatop-enable-bit = <0>;
667 reg_arm: regulator-vddcore {
668 compatible = "fsl,anatop-regulator";
669 regulator-name = "vddarm";
670 regulator-min-microvolt = <725000>;
671 regulator-max-microvolt = <1450000>;
672 regulator-always-on;
673 anatop-reg-offset = <0x140>;
674 anatop-vol-bit-shift = <0>;
675 anatop-vol-bit-width = <5>;
676 anatop-delay-reg-offset = <0x170>;
677 anatop-delay-bit-shift = <24>;
678 anatop-delay-bit-width = <2>;
679 anatop-min-bit-val = <1>;
680 anatop-min-voltage = <725000>;
681 anatop-max-voltage = <1450000>;
684 reg_pcie: regulator-vddpcie {
685 compatible = "fsl,anatop-regulator";
686 regulator-name = "vddpcie";
687 regulator-min-microvolt = <725000>;
688 regulator-max-microvolt = <1450000>;
689 anatop-reg-offset = <0x140>;
690 anatop-vol-bit-shift = <9>;
691 anatop-vol-bit-width = <5>;
692 anatop-delay-reg-offset = <0x170>;
693 anatop-delay-bit-shift = <26>;
694 anatop-delay-bit-width = <2>;
695 anatop-min-bit-val = <1>;
696 anatop-min-voltage = <725000>;
697 anatop-max-voltage = <1450000>;
700 reg_soc: regulator-vddsoc {
701 compatible = "fsl,anatop-regulator";
702 regulator-name = "vddsoc";
703 regulator-min-microvolt = <725000>;
704 regulator-max-microvolt = <1450000>;
705 regulator-always-on;
706 anatop-reg-offset = <0x140>;
707 anatop-vol-bit-shift = <18>;
708 anatop-vol-bit-width = <5>;
709 anatop-delay-reg-offset = <0x170>;
710 anatop-delay-bit-shift = <28>;
711 anatop-delay-bit-width = <2>;
712 anatop-min-bit-val = <1>;
713 anatop-min-voltage = <725000>;
714 anatop-max-voltage = <1450000>;
718 compatible = "fsl,imx6sx-tempmon";
719 interrupt-parent = <&gpc>;
722 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
723 nvmem-cell-names = "calib", "temp_grade";
725 #thermal-sensor-cells = <0>;
730 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
734 phy-3p0-supply = <®_vdd3p0>;
739 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
743 phy-3p0-supply = <®_vdd3p0>;
748 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
751 snvs_rtc: snvs-rtc-lp {
752 compatible = "fsl,sec-v4.0-mon-rtc-lp";
758 snvs_poweroff: snvs-poweroff {
759 compatible = "syscon-poweroff";
767 snvs_pwrkey: snvs-powerkey {
768 compatible = "fsl,sec-v4.0-pwrkey";
772 wakeup-source;
787 src: reset-controller@20d8000 {
788 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
792 #reset-cells = <1>;
796 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
798 interrupt-controller;
799 #interrupt-cells = <3>;
801 interrupt-parent = <&intc>;
803 clock-names = "ipg";
806 #address-cells = <1>;
807 #size-cells = <0>;
809 power-domain@0 {
811 #power-domain-cells = <0>;
814 pd_pu: power-domain@1 {
816 #power-domain-cells = <0>;
817 power-supply = <®_soc>;
821 pd_disp: power-domain@2 {
823 #power-domain-cells = <0>;
833 pd_pci: power-domain@3 {
835 #power-domain-cells = <0>;
836 power-supply = <®_pcie>;
842 compatible = "fsl,imx6sx-iomuxc";
847 compatible = "fsl,imx6sx-iomuxc-gpr",
848 "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
849 #address-cells = <1>;
850 #size-cells = <1>;
854 compatible = "fsl,imx6sx-ldb";
857 clock-names = "ldb";
861 #address-cells = <1>;
862 #size-cells = <0>;
881 sdma: dma-controller@20ec000 {
882 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
887 clock-names = "ipg", "ahb";
888 #dma-cells = <3>;
890 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
895 compatible = "fsl,aips-bus", "simple-bus";
896 #address-cells = <1>;
897 #size-cells = <1>;
902 compatible = "fsl,sec-v4.0";
903 #address-cells = <1>;
904 #size-cells = <1>;
907 interrupt-parent = <&intc>;
912 clock-names = "mem", "aclk", "ipg", "emi_slow";
915 compatible = "fsl,sec-v4.0-job-ring";
921 compatible = "fsl,sec-v4.0-job-ring";
928 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
934 ahb-burst-config = <0x0>;
935 tx-burst-size-dword = <0x10>;
936 rx-burst-size-dword = <0x10>;
941 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
947 ahb-burst-config = <0x0>;
948 tx-burst-size-dword = <0x10>;
949 rx-burst-size-dword = <0x10>;
954 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
962 ahb-burst-config = <0x0>;
963 tx-burst-size-dword = <0x10>;
964 rx-burst-size-dword = <0x10>;
969 #index-cells = <1>;
970 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
976 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
978 interrupt-names = "int0", "pps";
986 clock-names = "ipg", "ahb", "ptp",
988 fsl,num-tx-queues = <3>;
989 fsl,num-rx-queues = <3>;
990 fsl,stop-mode = <&gpr 0x10 3>;
1004 compatible = "fsl,imx6sx-usdhc";
1010 clock-names = "ipg", "ahb", "per";
1011 bus-width = <4>;
1012 fsl,tuning-start-tap = <20>;
1013 fsl,tuning-step = <2>;
1018 compatible = "fsl,imx6sx-usdhc";
1024 clock-names = "ipg", "ahb", "per";
1025 bus-width = <4>;
1026 fsl,tuning-start-tap = <20>;
1027 fsl,tuning-step = <2>;
1032 compatible = "fsl,imx6sx-usdhc";
1038 clock-names = "ipg", "ahb", "per";
1039 bus-width = <4>;
1040 fsl,tuning-start-tap = <20>;
1041 fsl,tuning-step = <2>;
1046 compatible = "fsl,imx6sx-usdhc";
1052 clock-names = "ipg", "ahb", "per";
1053 bus-width = <4>;
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1068 #address-cells = <1>;
1069 #size-cells = <0>;
1070 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1080 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1087 memory-controller@21b0000 {
1088 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1094 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1096 interrupt-names = "int0", "pps";
1104 clock-names = "ipg", "ahb", "ptp",
1106 fsl,stop-mode = <&gpr 0x10 4>;
1110 weim: memory-controller@21b8000 {
1111 #address-cells = <2>;
1112 #size-cells = <1>;
1113 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1117 fsl,weim-cs-gpr = <&gpr>;
1122 #address-cells = <1>;
1123 #size-cells = <1>;
1124 compatible = "fsl,imx6sx-ocotp", "syscon";
1128 cpu_speed_grade: speed-grade@10 {
1136 tempmon_temp_grade: temp-grade@20 {
1142 compatible = "fsl,imx6sx-sai";
1148 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1149 dma-names = "rx", "tx";
1155 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1161 compatible = "fsl,imx6sx-sai";
1167 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1168 dma-names = "rx", "tx";
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1176 compatible = "fsl,imx6sx-qspi";
1178 reg-names = "QuadSPI", "QuadSPI-memory";
1182 clock-names = "qspi_en", "qspi";
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1189 compatible = "fsl,imx6sx-qspi";
1191 reg-names = "QuadSPI", "QuadSPI-memory";
1195 clock-names = "qspi_en", "qspi";
1200 compatible = "fsl,imx6sx-uart",
1201 "fsl,imx6q-uart", "fsl,imx21-uart";
1206 clock-names = "ipg", "per";
1208 dma-names = "rx", "tx";
1213 compatible = "fsl,imx6sx-uart",
1214 "fsl,imx6q-uart", "fsl,imx21-uart";
1219 clock-names = "ipg", "per";
1221 dma-names = "rx", "tx";
1226 compatible = "fsl,imx6sx-uart",
1227 "fsl,imx6q-uart", "fsl,imx21-uart";
1232 clock-names = "ipg", "per";
1234 dma-names = "rx", "tx";
1239 compatible = "fsl,imx6sx-uart",
1240 "fsl,imx6q-uart", "fsl,imx21-uart";
1245 clock-names = "ipg", "per";
1247 dma-names = "rx", "tx";
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1263 compatible = "fsl,aips-bus", "simple-bus";
1264 #address-cells = <1>;
1265 #size-cells = <1>;
1269 spba-bus@2240000 {
1270 compatible = "fsl,spba-bus", "simple-bus";
1271 #address-cells = <1>;
1272 #size-cells = <1>;
1282 clock-names = "disp-axi", "csi_mclk", "dcic";
1287 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1291 clock-names = "axi";
1292 power-domains = <&pd_disp>;
1302 clock-names = "disp-axi", "csi_mclk", "dcic";
1307 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1313 clock-names = "pix", "axi", "disp_axi";
1314 assigned-clocks = <&clks IMX6SX_CLK_LCDIF1_PRE_SEL>,
1316 assigned-clock-parents = <&clks IMX6SX_CLK_PLL5_VIDEO_DIV>,
1318 power-domains = <&pd_disp>;
1328 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1334 clock-names = "pix", "axi", "disp_axi";
1335 power-domains = <&pd_disp>;
1341 reg-names = "vadc-vafe", "vadc-vdec";
1344 clock-names = "vadc", "csi";
1345 power-domains = <&pd_disp>;
1351 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1355 clock-names = "adc";
1356 fsl,adck-max-frequency = <30000000>, <40000000>,
1362 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1366 clock-names = "adc";
1367 fsl,adck-max-frequency = <30000000>, <40000000>,
1373 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1383 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1388 clock-names = "ipg", "per";
1393 compatible = "fsl,imx6sx-uart",
1394 "fsl,imx6q-uart", "fsl,imx21-uart";
1399 clock-names = "ipg", "per";
1401 dma-names = "rx", "tx";
1406 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1411 clock-names = "ipg", "per";
1412 #pwm-cells = <3>;
1416 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1421 clock-names = "ipg", "per";
1422 #pwm-cells = <3>;
1426 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1431 clock-names = "ipg", "per";
1432 #pwm-cells = <3>;
1436 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1441 clock-names = "ipg", "per";
1442 #pwm-cells = <3>;
1447 compatible = "fsl,imx6sx-pcie";
1449 reg-names = "dbi", "config";
1450 #address-cells = <3>;
1451 #size-cells = <2>;
1453 bus-range = <0x00 0xff>;
1455 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1456 num-lanes = <1>;
1458 interrupt-names = "msi";
1459 #interrupt-cells = <1>;
1460 interrupt-map-mask = <0 0 0 0x7>;
1461 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1469 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1470 power-domains = <&pd_disp>, <&pd_pci>;
1471 power-domain-names = "pcie", "pcie_phy";