Lines Matching +full:1 +full:a01000
12 #address-cells = <1>;
13 #size-cells = <1>;
60 #address-cells = <1>;
158 #address-cells = <1>;
159 #size-cells = <1>;
168 #address-cells = <1>;
169 #size-cells = <1>;
177 #address-cells = <1>;
178 #size-cells = <1>;
182 intc: interrupt-controller@a01000 {
219 #dma-cells = <1>;
226 #address-cells = <1>;
227 #size-cells = <1>;
246 #address-cells = <1>;
247 #size-cells = <1>;
253 #address-cells = <1>;
254 #size-cells = <1>;
281 #address-cells = <1>;
293 #address-cells = <1>;
305 #address-cells = <1>;
317 #address-cells = <1>;
365 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
379 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
393 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
415 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
416 <&sdma 19 23 1>, <&sdma 20 23 1>,
417 <&sdma 21 23 1>, <&sdma 22 23 1>;
473 fsl,stop-mode = <&gpr 0x10 1>;
609 #clock-cells = <1>;
622 reg_vdd1p1: regulator-1p1 {
679 anatop-min-bit-val = <1>;
695 anatop-min-bit-val = <1>;
712 anatop-min-bit-val = <1>;
792 #reset-cells = <1>;
806 #address-cells = <1>;
814 pd_pu: power-domain@1 {
815 reg = <1>;
849 #address-cells = <1>;
850 #size-cells = <1>;
861 #address-cells = <1>;
871 port@1 {
872 reg = <1>;
896 #address-cells = <1>;
897 #size-cells = <1>;
903 #address-cells = <1>;
904 #size-cells = <1>;
946 fsl,usbmisc = <&usbmisc 1>;
969 #index-cells = <1>;
1058 #address-cells = <1>;
1068 #address-cells = <1>;
1078 #address-cells = <1>;
1112 #size-cells = <1>;
1122 #address-cells = <1>;
1123 #size-cells = <1>;
1174 #address-cells = <1>;
1187 #address-cells = <1>;
1252 #address-cells = <1>;
1264 #address-cells = <1>;
1265 #size-cells = <1>;
1271 #address-cells = <1>;
1272 #size-cells = <1>;
1381 #address-cells = <1>;
1456 num-lanes = <1>;
1459 #interrupt-cells = <1>;
1461 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,