Lines Matching +full:0 +full:x00900000

17 		#size-cells = <0>;
19 		cpu0: cpu@0 {
22 			reg = <0>;
165 			reg = <0x00900000 0x40000>;
166 			ranges = <0 0x00900000 0x40000>;
176 					#size-cells = <0>;
178 					reg = <0x02018000 0x4000>;
179 					interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
192 			reg = <0x02200000 0x4000>;
193 			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
203 			reg = <0x02204000 0x4000>;
204 			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
214 			#size-cells = <0>;
216 			reg = <0x02800000 0x400000>;
217 			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
218 				     <0 7 IRQ_TYPE_LEVEL_HIGH>;
225 			ipu2_csi0: port@0 {
226 				reg = <0>;
243 				#size-cells = <0>;
246 				ipu2_di0_disp0: endpoint@0 {
247 					reg = <0>;
273 				#size-cells = <0>;
311 	gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
320 	gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
325 	gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
333 	gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
338 	gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
344 	gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
350 		mux-controls = <&mux 0>;
352 		#size-cells = <0>;
354 		port@0 {
355 			reg = <0>;
382 		#size-cells = <0>;
384 		port@0 {
385 			reg = <0>;
450 	lvds-channel@0 {
542 	mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
543 			<0x04 0x00100000>, /* MIPI_IPU2_MUX */
544 			<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
545 			<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
546 			<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
547 			<0x28 0x00000003>, /* DCIC1_MUX_CTL */
548 			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */