Lines Matching +full:0 +full:x00900000

16 		#size-cells = <0>;
18 		cpu0: cpu@0 {
21 			reg = <0>;
86 			reg = <0x00900000 0x20000>;
87 			ranges = <0 0x00900000 0x20000>;
95 				reg = <0x020f0000 0x4000>;
96 				interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
100 				reg = <0x020f4000 0x4000>;
101 				interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
108 				#size-cells = <0>;
110 				reg = <0x021f8000 0x4000>;
111 				interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
130 	gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10 189 2>,
140 	gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16  74 1>,
148 	gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
161 	gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4 76 1>,
168 	gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc  7 156 1>,
177 	gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2 196 1>,
185 		mux-controls = <&mux 0>;
187 		#size-cells = <0>;
189 		port@0 {
190 			reg = <0>;
241 		#size-cells = <0>;
243 		port@0 {
244 			reg = <0>;
323 		#size-cells = <0>;
325 		mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
326 			reg = <0>;
339 		#size-cells = <0>;
341 		mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
342 			reg = <0>;
355 		#size-cells = <0>;
357 		mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
358 			reg = <0>;
371 		#size-cells = <0>;
373 		mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
374 			reg = <0>;
386 	mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
387 			<0x34 0x00000038>, /* IPU_CSI1_MUX */
388 			<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
389 			<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
390 			<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
391 			<0x28 0x00000003>, /* DCIC1_MUX_CTL */
392 			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */