Lines Matching +full:0 +full:xfffffe00
36 #size-cells = <0>;
38 cpu@0 {
40 reg = <0>;
48 #clock-cells = <0>;
53 #clock-cells = <0>;
59 reg = <0x300000 0x10000>;
60 ranges = <0 0x300000 0x10000>;
73 reg = <0x80000000 0x300>;
74 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
84 reg = <0x90000000 0x300>;
85 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
102 reg = <0xf0000000 0x200>;
103 ranges = <0x0 0xf0000000 0x800>;
111 reg = <0x200 0x200>;
116 (AT91_XDMAC_DT_MEM_IF(0) |
120 (AT91_XDMAC_DT_MEM_IF(0) |
133 reg = <0x400 0x200>;
136 #size-cells = <0>;
140 (AT91_XDMAC_DT_MEM_IF(0) |
144 (AT91_XDMAC_DT_MEM_IF(0) |
154 reg = <0x600 0x200>;
157 #size-cells = <0>;
160 (AT91_XDMAC_DT_MEM_IF(0) |
164 (AT91_XDMAC_DT_MEM_IF(0) |
175 reg = <0xf0004000 0x200>;
176 ranges = <0x0 0xf0004000 0x800>;
184 reg = <0x200 0x200>;
189 (AT91_XDMAC_DT_MEM_IF(0) |
193 (AT91_XDMAC_DT_MEM_IF(0) |
206 reg = <0x400 0x200>;
209 #size-cells = <0>;
213 (AT91_XDMAC_DT_MEM_IF(0) |
217 (AT91_XDMAC_DT_MEM_IF(0) |
227 reg = <0x600 0x200>;
230 #size-cells = <0>;
233 (AT91_XDMAC_DT_MEM_IF(0) |
237 (AT91_XDMAC_DT_MEM_IF(0) |
248 reg = <0xf0008000 0x1000>;
249 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
258 reg = <0xf0010000 0x4000>;
263 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
266 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
274 reg = <0xf001c000 0x100>;
279 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
282 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
290 reg = <0xf0020000 0x200>;
291 ranges = <0x0 0xf0020000 0x800>;
299 reg = <0x200 0x200>;
304 (AT91_XDMAC_DT_MEM_IF(0) |
308 (AT91_XDMAC_DT_MEM_IF(0) |
321 reg = <0x600 0x200>;
324 #size-cells = <0>;
327 (AT91_XDMAC_DT_MEM_IF(0) |
331 (AT91_XDMAC_DT_MEM_IF(0) |
342 reg = <0xf0024000 0x200>;
343 ranges = <0x0 0xf0024000 0x800>;
351 reg = <0x200 0x200>;
356 (AT91_XDMAC_DT_MEM_IF(0) |
360 (AT91_XDMAC_DT_MEM_IF(0) |
373 reg = <0x600 0x200>;
376 #size-cells = <0>;
379 (AT91_XDMAC_DT_MEM_IF(0) |
383 (AT91_XDMAC_DT_MEM_IF(0) |
394 reg = <0xf0028000 0x100>;
402 reg = <0xf002c000 0x100>;
403 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
407 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
414 reg = <0xf0030000 0x100>;
415 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
422 reg = <0xf0034000 0x100>;
423 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
427 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
430 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
437 reg = <0xf0038000 0x100>;
438 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
442 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
445 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
452 reg = <0xf003c000 0x100>;
457 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
465 reg = <0xf0040000 0x100>;
473 reg = <0xf8000000 0x100>, <0x300000 0x7800>;
475 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>,
476 <68 IRQ_TYPE_LEVEL_HIGH 0>;
483 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
489 reg = <0xf8004000 0x100>, <0x300000 0xbc00>;
491 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>,
492 <69 IRQ_TYPE_LEVEL_HIGH 0>;
499 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
505 reg = <0xf8008000 0x100>;
507 #size-cells = <0>;
508 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
509 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk32k 0>;
515 reg = <0xf8010000 0x200>;
516 ranges = <0x0 0xf8010000 0x800>;
524 reg = <0x200 0x200>;
529 (AT91_XDMAC_DT_MEM_IF(0) |
533 (AT91_XDMAC_DT_MEM_IF(0) |
546 reg = <0x600 0x200>;
549 #size-cells = <0>;
552 (AT91_XDMAC_DT_MEM_IF(0) |
556 (AT91_XDMAC_DT_MEM_IF(0) |
567 reg = <0xf8014000 0x200>;
568 ranges = <0x0 0xf8014000 0x800>;
576 reg = <0x200 0x200>;
581 (AT91_XDMAC_DT_MEM_IF(0) |
585 (AT91_XDMAC_DT_MEM_IF(0) |
598 reg = <0x600 0x200>;
601 #size-cells = <0>;
604 (AT91_XDMAC_DT_MEM_IF(0) |
608 (AT91_XDMAC_DT_MEM_IF(0) |
619 reg = <0xf8018000 0x200>;
620 ranges = <0x0 0xf8018000 0x800>;
628 reg = <0x200 0x200>;
633 (AT91_XDMAC_DT_MEM_IF(0) |
637 (AT91_XDMAC_DT_MEM_IF(0) |
650 reg = <0x600 0x200>;
653 #size-cells = <0>;
656 (AT91_XDMAC_DT_MEM_IF(0) |
660 (AT91_XDMAC_DT_MEM_IF(0) |
671 reg = <0xf801c000 0x200>;
672 ranges = <0x0 0xf801c000 0x800>;
680 reg = <0x200 0x200>;
685 (AT91_XDMAC_DT_MEM_IF(0) |
687 AT91_XDMAC_DT_PERID(0))>,
689 (AT91_XDMAC_DT_MEM_IF(0) |
702 reg = <0x400 0x200>;
705 #size-cells = <0>;
709 (AT91_XDMAC_DT_MEM_IF(0) |
711 AT91_XDMAC_DT_PERID(0))>,
713 (AT91_XDMAC_DT_MEM_IF(0) |
723 reg = <0x600 0x200>;
726 #size-cells = <0>;
729 (AT91_XDMAC_DT_MEM_IF(0) |
731 AT91_XDMAC_DT_PERID(0))>,
733 (AT91_XDMAC_DT_MEM_IF(0) |
744 reg = <0xf8020000 0x200>;
745 ranges = <0x0 0xf8020000 0x800>;
753 reg = <0x200 0x200>;
758 (AT91_XDMAC_DT_MEM_IF(0) |
762 (AT91_XDMAC_DT_MEM_IF(0) |
775 reg = <0x400 0x200>;
778 #size-cells = <0>;
782 (AT91_XDMAC_DT_MEM_IF(0) |
786 (AT91_XDMAC_DT_MEM_IF(0) |
796 reg = <0x600 0x200>;
799 #size-cells = <0>;
802 (AT91_XDMAC_DT_MEM_IF(0) |
806 (AT91_XDMAC_DT_MEM_IF(0) |
817 reg = <0xf8024000 0x200>;
818 ranges = <0x0 0xf8024000 0x800>;
826 reg = <0x200 0x200>;
831 (AT91_XDMAC_DT_MEM_IF(0) |
835 (AT91_XDMAC_DT_MEM_IF(0) |
848 reg = <0x400 0x200>;
851 #size-cells = <0>;
855 (AT91_XDMAC_DT_MEM_IF(0) |
859 (AT91_XDMAC_DT_MEM_IF(0) |
869 reg = <0x600 0x200>;
872 #size-cells = <0>;
875 (AT91_XDMAC_DT_MEM_IF(0) |
879 (AT91_XDMAC_DT_MEM_IF(0) |
890 reg = <0xf8028000 0x200>;
891 ranges = <0x0 0xf8028000 0x800>;
899 reg = <0x200 0x200>;
904 (AT91_XDMAC_DT_MEM_IF(0) |
908 (AT91_XDMAC_DT_MEM_IF(0) |
921 reg = <0x400 0x200>;
924 #size-cells = <0>;
928 (AT91_XDMAC_DT_MEM_IF(0) |
932 (AT91_XDMAC_DT_MEM_IF(0) |
942 reg = <0x600 0x200>;
945 #size-cells = <0>;
948 (AT91_XDMAC_DT_MEM_IF(0) |
952 (AT91_XDMAC_DT_MEM_IF(0) |
963 reg = <0xf802c000 0x1000>;
964 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */
979 reg = <0xf8034000 0x300>;
988 reg = <0xf8040000 0x200>;
989 ranges = <0x0 0xf8040000 0x800>;
997 reg = <0x200 0x200>;
1002 (AT91_XDMAC_DT_MEM_IF(0) |
1006 (AT91_XDMAC_DT_MEM_IF(0) |
1019 reg = <0x600 0x200>;
1022 #size-cells = <0>;
1025 (AT91_XDMAC_DT_MEM_IF(0) |
1029 (AT91_XDMAC_DT_MEM_IF(0) |
1040 reg = <0xf8044000 0x200>;
1041 ranges = <0x0 0xf8044000 0x800>;
1049 reg = <0x200 0x200>;
1054 (AT91_XDMAC_DT_MEM_IF(0) |
1058 (AT91_XDMAC_DT_MEM_IF(0) |
1071 reg = <0x600 0x200>;
1074 #size-cells = <0>;
1077 (AT91_XDMAC_DT_MEM_IF(0) |
1081 (AT91_XDMAC_DT_MEM_IF(0) |
1092 reg = <0xffffde00 0x200>;
1097 reg = <0xffffe000 0x300>, <0xffffe600 0x100>;
1102 reg = <0xffffe800 0x200>;
1109 reg = <0xffffea00 0x100>;
1114 reg = <0xfffff100 0x100>;
1122 reg = <0xfffff200 0x200>;
1127 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1130 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1139 ranges = <0xfffff400 0xfffff400 0x800>;
1146 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */
1147 0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000 /* pioB */
1148 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */
1149 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */
1154 reg = <0xfffff400 0x200>;
1165 reg = <0xfffff600 0x200>;
1177 reg = <0xfffff800 0x200>;
1188 reg = <0xfffffa00 0x200>;
1201 reg = <0xfffffc00 0x200>;
1204 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
1210 reg = <0xfffffe00 0x10>;
1211 clocks = <&clk32k 0>;
1216 reg = <0xfffffe10 0x10>;
1218 #size-cells = <0>;
1219 clocks = <&clk32k 0>;
1227 reg = <0xfffffe20 0x20>;
1229 clocks = <&clk32k 0>;
1234 reg = <0xfffffe50 0x4>;
1241 reg = <0xfffffe60 0x10>;
1246 reg = <0xfffffea8 0x100>;
1248 clocks = <&clk32k 0>;
1253 reg = <0xffffff80 0x24>;