Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x03ffffff
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/clock/at91.h>
15 #include <dt-bindings/mfd/at91-usart.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
23 interrupt-parent = <&aic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
39 cpu@0 {
40 compatible = "arm,arm926ej-s";
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
64 compatible = "mmio-sram";
65 reg = <0x00300000 0x100000>;
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges = <0 0x00300000 0x100000>;
72 compatible = "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <1>;
78 #address-cells = <1>;
79 #size-cells = <0>;
80 compatible = "microchip,sam9x60-udc";
81 reg = <0x00500000 0x100000
82 0xf803c000 0x400>;
85 clock-names = "pclk", "hclk";
86 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
87 assigned-clock-rates = <480000000>;
92 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
93 reg = <0x00600000 0x100000>;
96 clock-names = "ohci_clk", "hclk", "uhpck";
101 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
102 reg = <0x00700000 0x100000>;
105 clock-names = "usb_clk", "ehci_clk";
106 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
107 assigned-clock-rates = <480000000>;
112 compatible = "microchip,sam9x60-ebi";
113 #address-cells = <2>;
114 #size-cells = <1>;
117 reg = <0x10000000 0x60000000>;
118 ranges = <0x0 0x0 0x10000000 0x10000000
119 0x1 0x0 0x20000000 0x10000000
120 0x2 0x0 0x30000000 0x10000000
121 0x3 0x0 0x40000000 0x10000000
122 0x4 0x0 0x50000000 0x10000000
123 0x5 0x0 0x60000000 0x10000000>;
127 nand_controller: nand-controller {
128 compatible = "microchip,sam9x60-nand-controller";
129 ecc-engine = <&pmecc>;
130 #address-cells = <2>;
131 #size-cells = <1>;
137 sdmmc0: sdio-host@80000000 {
138 compatible = "microchip,sam9x60-sdhci";
139 reg = <0x80000000 0x300>;
140 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
142 clock-names = "hclock", "multclk";
143 assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
144 assigned-clock-rates = <100000000>;
148 sdmmc1: sdio-host@90000000 {
149 compatible = "microchip,sam9x60-sdhci";
150 reg = <0x90000000 0x300>;
151 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
153 clock-names = "hclock", "multclk";
154 assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
155 assigned-clock-rates = <100000000>;
160 compatible = "simple-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
166 compatible = "atmel,sama5d2-flexcom";
167 reg = <0xf0000000 0x200>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges = <0x0 0xf0000000 0x800>;
175 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
176 reg = <0x200 0x200>;
179 (AT91_XDMAC_DT_MEM_IF(0) |
183 (AT91_XDMAC_DT_MEM_IF(0) |
186 dma-names = "tx", "rx";
188 clock-names = "usart";
189 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
190 atmel,use-dma-rx;
191 atmel,use-dma-tx;
192 atmel,fifo-size = <16>;
197 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
198 reg = <0x400 0x200>;
200 #address-cells = <1>;
201 #size-cells = <0>;
203 clock-names = "spi_clk";
205 (AT91_XDMAC_DT_MEM_IF(0) |
209 (AT91_XDMAC_DT_MEM_IF(0) |
212 dma-names = "tx", "rx";
213 atmel,fifo-size = <16>;
218 compatible = "microchip,sam9x60-i2c";
219 reg = <0x600 0x200>;
221 #address-cells = <1>;
222 #size-cells = <0>;
225 (AT91_XDMAC_DT_MEM_IF(0) |
229 (AT91_XDMAC_DT_MEM_IF(0) |
232 dma-names = "tx", "rx";
233 atmel,fifo-size = <16>;
239 compatible = "atmel,sama5d2-flexcom";
240 reg = <0xf0004000 0x200>;
242 #address-cells = <1>;
243 #size-cells = <1>;
244 ranges = <0x0 0xf0004000 0x800>;
248 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
249 reg = <0x200 0x200>;
250 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
253 (AT91_XDMAC_DT_MEM_IF(0) |
257 (AT91_XDMAC_DT_MEM_IF(0) |
260 dma-names = "tx", "rx";
262 clock-names = "usart";
263 atmel,use-dma-rx;
264 atmel,use-dma-tx;
265 atmel,fifo-size = <16>;
270 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
271 reg = <0x400 0x200>;
273 #address-cells = <1>;
274 #size-cells = <0>;
276 clock-names = "spi_clk";
278 (AT91_XDMAC_DT_MEM_IF(0) |
282 (AT91_XDMAC_DT_MEM_IF(0) |
285 dma-names = "tx", "rx";
286 atmel,fifo-size = <16>;
291 compatible = "microchip,sam9x60-i2c";
292 reg = <0x600 0x200>;
294 #address-cells = <1>;
295 #size-cells = <0>;
298 (AT91_XDMAC_DT_MEM_IF(0) |
302 (AT91_XDMAC_DT_MEM_IF(0) |
305 dma-names = "tx", "rx";
306 atmel,fifo-size = <16>;
311 dma0: dma-controller@f0008000 {
312 compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
313 reg = <0xf0008000 0x1000>;
314 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
315 #dma-cells = <1>;
317 clock-names = "dma_clk";
321 compatible = "atmel,at91sam9g45-ssc";
322 reg = <0xf0010000 0x4000>;
325 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
328 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
330 dma-names = "tx", "rx";
332 clock-names = "pclk";
337 compatible = "microchip,sam9x60-qspi";
338 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
339 reg-names = "qspi_base", "qspi_mmap";
342 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
345 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
347 dma-names = "tx", "rx";
349 clock-names = "pclk", "qspick";
351 #address-cells = <1>;
352 #size-cells = <0>;
357 compatible = "microchip,sam9x60-i2smcc";
358 reg = <0xf001c000 0x100>;
361 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
364 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
366 dma-names = "tx", "rx";
368 clock-names = "pclk", "gclk";
373 compatible = "atmel,sama5d2-flexcom";
374 reg = <0xf0020000 0x200>;
376 #address-cells = <1>;
377 #size-cells = <1>;
378 ranges = <0x0 0xf0020000 0x800>;
382 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
383 reg = <0x200 0x200>;
386 (AT91_XDMAC_DT_MEM_IF(0) |
390 (AT91_XDMAC_DT_MEM_IF(0) |
393 dma-names = "tx", "rx";
395 clock-names = "usart";
396 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
397 atmel,use-dma-rx;
398 atmel,use-dma-tx;
399 atmel,fifo-size = <16>;
404 compatible = "microchip,sam9x60-i2c";
405 reg = <0x600 0x200>;
407 #address-cells = <1>;
408 #size-cells = <0>;
411 (AT91_XDMAC_DT_MEM_IF(0) |
415 (AT91_XDMAC_DT_MEM_IF(0) |
418 dma-names = "tx", "rx";
419 atmel,fifo-size = <16>;
425 compatible = "atmel,sama5d2-flexcom";
426 reg = <0xf0024000 0x200>;
428 #address-cells = <1>;
429 #size-cells = <1>;
430 ranges = <0x0 0xf0024000 0x800>;
434 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
435 reg = <0x200 0x200>;
438 (AT91_XDMAC_DT_MEM_IF(0) |
442 (AT91_XDMAC_DT_MEM_IF(0) |
445 dma-names = "tx", "rx";
447 clock-names = "usart";
448 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
449 atmel,use-dma-rx;
450 atmel,use-dma-tx;
451 atmel,fifo-size = <16>;
456 compatible = "microchip,sam9x60-i2c";
457 reg = <0x600 0x200>;
459 #address-cells = <1>;
460 #size-cells = <0>;
463 (AT91_XDMAC_DT_MEM_IF(0) |
467 (AT91_XDMAC_DT_MEM_IF(0) |
470 dma-names = "tx", "rx";
471 atmel,fifo-size = <16>;
477 compatible = "microchip,sam9x60-pit64b";
478 reg = <0xf0028000 0x100>;
481 clock-names = "pclk", "gclk";
485 compatible = "atmel,at91sam9g46-sha";
486 reg = <0xf002c000 0x100>;
487 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
489 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
491 dma-names = "tx";
493 clock-names = "sha_clk";
497 compatible = "microchip,sam9x60-trng";
498 reg = <0xf0030000 0x100>;
499 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
504 compatible = "atmel,at91sam9g46-aes";
505 reg = <0xf0034000 0x100>;
506 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
508 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
511 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
513 dma-names = "tx", "rx";
515 clock-names = "aes_clk";
519 compatible = "atmel,at91sam9g46-tdes";
520 reg = <0xf0038000 0x100>;
521 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
523 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
526 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
528 dma-names = "tx", "rx";
530 clock-names = "tdes_clk";
534 compatible = "atmel,sama5d2-classd";
535 reg = <0xf003c000 0x100>;
538 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
540 dma-names = "tx";
542 clock-names = "pclk", "gclk";
547 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
548 reg = <0xf8000000 0x300>;
551 clock-names = "can_clk";
556 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
557 reg = <0xf8004000 0x300>;
560 clock-names = "can_clk";
565 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
566 #address-cells = <1>;
567 #size-cells = <0>;
568 reg = <0xf8008000 0x100>;
569 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
570 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
571 clock-names = "t0_clk", "slow_clk";
575 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
576 #address-cells = <1>;
577 #size-cells = <0>;
578 reg = <0xf800c000 0x100>;
579 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
580 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
581 clock-names = "t0_clk", "slow_clk";
585 compatible = "atmel,sama5d2-flexcom";
586 reg = <0xf8010000 0x200>;
588 #address-cells = <1>;
589 #size-cells = <1>;
590 ranges = <0x0 0xf8010000 0x800>;
594 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
595 reg = <0x200 0x200>;
598 (AT91_XDMAC_DT_MEM_IF(0) |
602 (AT91_XDMAC_DT_MEM_IF(0) |
605 dma-names = "tx", "rx";
607 clock-names = "usart";
608 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
609 atmel,use-dma-rx;
610 atmel,use-dma-tx;
611 atmel,fifo-size = <16>;
616 compatible = "microchip,sam9x60-i2c";
617 reg = <0x600 0x200>;
619 #address-cells = <1>;
620 #size-cells = <0>;
623 (AT91_XDMAC_DT_MEM_IF(0) |
627 (AT91_XDMAC_DT_MEM_IF(0) |
630 dma-names = "tx", "rx";
631 atmel,fifo-size = <16>;
637 compatible = "atmel,sama5d2-flexcom";
638 reg = <0xf8014000 0x200>;
640 #address-cells = <1>;
641 #size-cells = <1>;
642 ranges = <0x0 0xf8014000 0x800>;
646 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
647 reg = <0x200 0x200>;
650 (AT91_XDMAC_DT_MEM_IF(0) |
654 (AT91_XDMAC_DT_MEM_IF(0) |
657 dma-names = "tx", "rx";
659 clock-names = "usart";
660 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
661 atmel,use-dma-rx;
662 atmel,use-dma-tx;
663 atmel,fifo-size = <16>;
668 compatible = "microchip,sam9x60-i2c";
669 reg = <0x600 0x200>;
671 #address-cells = <1>;
672 #size-cells = <0>;
675 (AT91_XDMAC_DT_MEM_IF(0) |
679 (AT91_XDMAC_DT_MEM_IF(0) |
682 dma-names = "tx", "rx";
683 atmel,fifo-size = <16>;
689 compatible = "atmel,sama5d2-flexcom";
690 reg = <0xf8018000 0x200>;
692 #address-cells = <1>;
693 #size-cells = <1>;
694 ranges = <0x0 0xf8018000 0x800>;
698 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
699 reg = <0x200 0x200>;
702 (AT91_XDMAC_DT_MEM_IF(0) |
706 (AT91_XDMAC_DT_MEM_IF(0) |
709 dma-names = "tx", "rx";
711 clock-names = "usart";
712 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
713 atmel,use-dma-rx;
714 atmel,use-dma-tx;
715 atmel,fifo-size = <16>;
720 compatible = "microchip,sam9x60-i2c";
721 reg = <0x600 0x200>;
723 #address-cells = <1>;
724 #size-cells = <0>;
727 (AT91_XDMAC_DT_MEM_IF(0) |
731 (AT91_XDMAC_DT_MEM_IF(0) |
734 dma-names = "tx", "rx";
735 atmel,fifo-size = <16>;
741 compatible = "atmel,sama5d2-flexcom";
742 reg = <0xf801c000 0x200>;
744 #address-cells = <1>;
745 #size-cells = <1>;
746 ranges = <0x0 0xf801c000 0x800>;
750 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
751 reg = <0x200 0x200>;
754 (AT91_XDMAC_DT_MEM_IF(0) |
756 AT91_XDMAC_DT_PERID(0))>,
758 (AT91_XDMAC_DT_MEM_IF(0) |
761 dma-names = "tx", "rx";
763 clock-names = "usart";
764 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
765 atmel,use-dma-rx;
766 atmel,use-dma-tx;
767 atmel,fifo-size = <16>;
772 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
773 reg = <0x400 0x200>;
775 #address-cells = <1>;
776 #size-cells = <0>;
778 clock-names = "spi_clk";
780 (AT91_XDMAC_DT_MEM_IF(0) |
782 AT91_XDMAC_DT_PERID(0))>,
784 (AT91_XDMAC_DT_MEM_IF(0) |
787 dma-names = "tx", "rx";
788 atmel,fifo-size = <16>;
793 compatible = "microchip,sam9x60-i2c";
794 reg = <0x600 0x200>;
796 #address-cells = <1>;
797 #size-cells = <0>;
800 (AT91_XDMAC_DT_MEM_IF(0) |
802 AT91_XDMAC_DT_PERID(0))>,
804 (AT91_XDMAC_DT_MEM_IF(0) |
807 dma-names = "tx", "rx";
808 atmel,fifo-size = <16>;
814 compatible = "atmel,sama5d2-flexcom";
815 reg = <0xf8020000 0x200>;
817 #address-cells = <1>;
818 #size-cells = <1>;
819 ranges = <0x0 0xf8020000 0x800>;
823 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
824 reg = <0x200 0x200>;
827 (AT91_XDMAC_DT_MEM_IF(0) |
831 (AT91_XDMAC_DT_MEM_IF(0) |
834 dma-names = "tx", "rx";
836 clock-names = "usart";
837 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
838 atmel,use-dma-rx;
839 atmel,use-dma-tx;
840 atmel,fifo-size = <16>;
845 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
846 reg = <0x400 0x200>;
848 #address-cells = <1>;
849 #size-cells = <0>;
851 clock-names = "spi_clk";
853 (AT91_XDMAC_DT_MEM_IF(0) |
857 (AT91_XDMAC_DT_MEM_IF(0) |
860 dma-names = "tx", "rx";
861 atmel,fifo-size = <16>;
866 compatible = "microchip,sam9x60-i2c";
867 reg = <0x600 0x200>;
869 #address-cells = <1>;
870 #size-cells = <0>;
873 (AT91_XDMAC_DT_MEM_IF(0) |
877 (AT91_XDMAC_DT_MEM_IF(0) |
880 dma-names = "tx", "rx";
881 atmel,fifo-size = <16>;
887 compatible = "atmel,sama5d2-flexcom";
888 reg = <0xf8024000 0x200>;
890 #address-cells = <1>;
891 #size-cells = <1>;
892 ranges = <0x0 0xf8024000 0x800>;
896 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
897 reg = <0x200 0x200>;
900 (AT91_XDMAC_DT_MEM_IF(0) |
904 (AT91_XDMAC_DT_MEM_IF(0) |
907 dma-names = "tx", "rx";
909 clock-names = "usart";
910 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
911 atmel,use-dma-rx;
912 atmel,use-dma-tx;
913 atmel,fifo-size = <16>;
918 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
919 reg = <0x400 0x200>;
921 #address-cells = <1>;
922 #size-cells = <0>;
924 clock-names = "spi_clk";
926 (AT91_XDMAC_DT_MEM_IF(0) |
930 (AT91_XDMAC_DT_MEM_IF(0) |
933 dma-names = "tx", "rx";
934 atmel,fifo-size = <16>;
939 compatible = "microchip,sam9x60-i2c";
940 reg = <0x600 0x200>;
942 #address-cells = <1>;
943 #size-cells = <0>;
946 (AT91_XDMAC_DT_MEM_IF(0) |
950 (AT91_XDMAC_DT_MEM_IF(0) |
953 dma-names = "tx", "rx";
954 atmel,fifo-size = <16>;
960 compatible = "atmel,sama5d2-flexcom";
961 reg = <0xf8028000 0x200>;
963 #address-cells = <1>;
964 #size-cells = <1>;
965 ranges = <0x0 0xf8028000 0x800>;
969 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
970 reg = <0x200 0x200>;
973 (AT91_XDMAC_DT_MEM_IF(0) |
977 (AT91_XDMAC_DT_MEM_IF(0) |
980 dma-names = "tx", "rx";
982 clock-names = "usart";
983 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
984 atmel,use-dma-rx;
985 atmel,use-dma-tx;
986 atmel,fifo-size = <16>;
991 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
992 reg = <0x400 0x200>;
994 #address-cells = <1>;
995 #size-cells = <0>;
997 clock-names = "spi_clk";
999 (AT91_XDMAC_DT_MEM_IF(0) |
1003 (AT91_XDMAC_DT_MEM_IF(0) |
1006 dma-names = "tx", "rx";
1007 atmel,fifo-size = <16>;
1012 compatible = "microchip,sam9x60-i2c";
1013 reg = <0x600 0x200>;
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1019 (AT91_XDMAC_DT_MEM_IF(0) |
1023 (AT91_XDMAC_DT_MEM_IF(0) |
1026 dma-names = "tx", "rx";
1027 atmel,fifo-size = <16>;
1033 compatible = "cdns,sam9x60-macb", "cdns,macb";
1034 reg = <0xf802c000 0x1000>;
1037 clock-names = "hclk", "pclk";
1042 compatible = "cdns,sam9x60-macb", "cdns,macb";
1043 reg = <0xf8030000 0x1000>;
1046 clock-names = "hclk", "pclk";
1051 compatible = "microchip,sam9x60-pwm";
1052 reg = <0xf8034000 0x300>;
1055 #pwm-cells = <3>;
1060 compatible = "microchip,sam9x60-hlcdc";
1061 reg = <0xf8038000 0x4000>;
1062 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
1064 clock-names = "periph_clk","sys_clk", "slow_clk";
1065 assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
1066 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
1069 hlcdc-display-controller {
1070 compatible = "atmel,hlcdc-display-controller";
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1074 port@0 {
1075 #address-cells = <1>;
1076 #size-cells = <0>;
1077 reg = <0>;
1081 hlcdc_pwm: hlcdc-pwm {
1082 compatible = "atmel,hlcdc-pwm";
1083 #pwm-cells = <3>;
1088 compatible = "atmel,sama5d2-flexcom";
1089 reg = <0xf8040000 0x200>;
1091 #address-cells = <1>;
1092 #size-cells = <1>;
1093 ranges = <0x0 0xf8040000 0x800>;
1097 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
1098 reg = <0x200 0x200>;
1101 (AT91_XDMAC_DT_MEM_IF(0) |
1105 (AT91_XDMAC_DT_MEM_IF(0) |
1108 dma-names = "tx", "rx";
1110 clock-names = "usart";
1111 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
1112 atmel,use-dma-rx;
1113 atmel,use-dma-tx;
1114 atmel,fifo-size = <16>;
1119 compatible = "microchip,sam9x60-i2c";
1120 reg = <0x600 0x200>;
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1126 (AT91_XDMAC_DT_MEM_IF(0) |
1130 (AT91_XDMAC_DT_MEM_IF(0) |
1133 dma-names = "tx", "rx";
1134 atmel,fifo-size = <16>;
1140 compatible = "atmel,sama5d2-flexcom";
1141 reg = <0xf8044000 0x200>;
1143 #address-cells = <1>;
1144 #size-cells = <1>;
1145 ranges = <0x0 0xf8044000 0x800>;
1149 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
1150 reg = <0x200 0x200>;
1153 (AT91_XDMAC_DT_MEM_IF(0) |
1157 (AT91_XDMAC_DT_MEM_IF(0) |
1160 dma-names = "tx", "rx";
1162 clock-names = "usart";
1163 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
1164 atmel,use-dma-rx;
1165 atmel,use-dma-tx;
1166 atmel,fifo-size = <16>;
1171 compatible = "microchip,sam9x60-i2c";
1172 reg = <0x600 0x200>;
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1178 (AT91_XDMAC_DT_MEM_IF(0) |
1182 (AT91_XDMAC_DT_MEM_IF(0) |
1185 dma-names = "tx", "rx";
1186 atmel,fifo-size = <16>;
1192 compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
1193 reg = <0xf8048000 0x100>;
1196 clock-names = "isi_clk";
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1205 compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
1206 reg = <0xf804c000 0x100>;
1209 clock-names = "adc_clk";
1210 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
1211 dma-names = "rx";
1212 atmel,min-sample-rate-hz = <200000>;
1213 atmel,max-sample-rate-hz = <20000000>;
1214 atmel,startup-time-ms = <4>;
1215 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1216 #io-channel-cells = <1>;
1221 compatible = "microchip,sam9x60-sfr", "syscon";
1222 reg = <0xf8050000 0x100>;
1226 compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
1227 reg = <0xffffde00 0x200>;
1230 pmecc: ecc-engine@ffffe000 {
1231 compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
1232 reg = <0xffffe000 0x300>,
1233 <0xffffe600 0x100>;
1237 compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
1238 reg = <0xffffe800 0x200>;
1240 clock-names = "ddrck", "mpddr";
1244 compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
1245 reg = <0xffffea00 0x100>;
1248 aic: interrupt-controller@fffff100 {
1249 compatible = "microchip,sam9x60-aic";
1250 #interrupt-cells = <3>;
1251 interrupt-controller;
1252 reg = <0xfffff100 0x100>;
1253 atmel,external-irqs = <31>;
1257 …compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel…
1258 reg = <0xfffff200 0x200>;
1259 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
1262 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1265 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1267 dma-names = "tx", "rx";
1269 clock-names = "usart";
1274 #address-cells = <1>;
1275 #size-cells = <1>;
1276 compatible = "microchip,sam9x60-pinctrl", "simple-mfd";
1277 ranges = <0xfffff400 0xfffff400 0x800>;
1279 /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
1280 atmel,mux-mask = <
1282 0xffffffff 0xffe03fff 0xef00019d /* pioA */
1283 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
1284 0xffffffff 0xffffffff 0xf83fffff /* pioC */
1285 0x003fffff 0x003f8000 0x00000000 /* pioD */
1289 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
1290 reg = <0xfffff400 0x200>;
1292 #gpio-cells = <2>;
1293 gpio-controller;
1294 interrupt-controller;
1295 #interrupt-cells = <2>;
1300 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
1301 reg = <0xfffff600 0x200>;
1303 #gpio-cells = <2>;
1304 gpio-controller;
1305 #gpio-lines = <26>;
1306 interrupt-controller;
1307 #interrupt-cells = <2>;
1312 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
1313 reg = <0xfffff800 0x200>;
1315 #gpio-cells = <2>;
1316 gpio-controller;
1317 interrupt-controller;
1318 #interrupt-cells = <2>;
1323 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio";
1324 reg = <0xfffffa00 0x200>;
1326 #gpio-cells = <2>;
1327 gpio-controller;
1328 #gpio-lines = <22>;
1329 interrupt-controller;
1330 #interrupt-cells = <2>;
1335 pmc: clock-controller@fffffc00 {
1336 compatible = "microchip,sam9x60-pmc", "syscon";
1337 reg = <0xfffffc00 0x200>;
1339 #clock-cells = <2>;
1340 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
1341 clock-names = "td_slck", "md_slck", "main_xtal";
1344 reset_controller: reset-controller@fffffe00 {
1345 compatible = "microchip,sam9x60-rstc";
1346 reg = <0xfffffe00 0x10>;
1347 clocks = <&clk32k 0>;
1351 compatible = "microchip,sam9x60-shdwc";
1352 reg = <0xfffffe10 0x10>;
1353 clocks = <&clk32k 0>;
1354 #address-cells = <1>;
1355 #size-cells = <0>;
1356 atmel,wakeup-rtc-timer;
1357 atmel,wakeup-rtt-timer;
1362 compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
1363 reg = <0xfffffe20 0x20>;
1369 compatible = "atmel,at91sam9260-pit";
1370 reg = <0xfffffe40 0x10>;
1375 clk32k: clock-controller@fffffe50 {
1376 compatible = "microchip,sam9x60-sckc";
1377 reg = <0xfffffe50 0x4>;
1379 #clock-cells = <1>;
1383 compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
1384 reg = <0xfffffe60 0x10>;
1388 compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
1389 reg = <0xfffffea8 0x100>;
1395 compatible = "microchip,sam9x60-wdt";
1396 reg = <0xffffff80 0x24>;
1398 clocks = <&clk32k 0>;